src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 '''
  43 footer = '''
  44    endmodule
  45 endpackage
  46 '''
  47
  48
  49 def pinmuxgen(pth=None, verify=True):
  50     """ populating the file with the code
  51     """
  52
  53     p = Parse(pth, verify)
  54     iocells = Interfaces()
  55     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  56     ifaces = Interfaces(pth)
  57     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  58     init(p, ifaces)
  59
  60     bp = 'bsv_src'
  61     if pth:
  62         bp = os.path.join(pth, bp)
  63     if not os.path.exists(bp):
  64         os.makedirs(bp)
  65     bl = os.path.join(bp, 'bsv_lib')
  66     if not os.path.exists(bl):
  67         os.makedirs(bl)
  68
  69     cwd = os.path.split(__file__)[0]
  70
  71     # copy over template and library files
  72     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  73                     os.path.join(bp, 'Makefile'))
  74     cwd = os.path.join(cwd, 'bsv_lib')
  75     for fname in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv',
  76                   'gpio.bsv',  'mux.bsv']:
  77         shutil.copyfile(os.path.join(cwd, fname),
  78                         os.path.join(bl, fname))
  79
  80     bus = os.path.join(bp, 'busenable.bsv')
  81     pmp = os.path.join(bp, 'pinmux.bsv')
  82     ptp = os.path.join(bp, 'PinTop.bsv')
  83     bvp = os.path.join(bp, 'bus.bsv')
  84     idef = os.path.join(bp, 'instance_defines.bsv')
  85
  86     write_pmp(pmp, p, ifaces, iocells)
  87     write_ptp(ptp, p, ifaces)
  88     write_bvp(bvp, p, ifaces)
  89     write_bus(bus, p, ifaces)
  90     write_instances(idef, p, ifaces)
  91
  92
  93 def write_bus(bus, p, ifaces):
  94     # package and interface declaration followed by
  95     # the generic io_cell definition
  96     with open(bus, "w") as bsv_file:
  97         ifaces.busfmt(bsv_file)
  98
  99
 100 def write_pmp(pmp, p, ifaces, iocells):
 101     # package and interface declaration followed by
 102     # the generic io_cell definition
 103     with open(pmp, "w") as bsv_file:
 104         bsv_file.write(header)
 105
 106         cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
 107         bsv_file.write('''\
 108    interface MuxSelectionLines;
 109
 110       // declare the method which will capture the user pin-mux
 111       // selection values.The width of the input is dependent on the number
 112       // of muxes happening per IO. For now we have a generalized width
 113       // where each IO will have the same number of muxes.''')
 114
 115         for cell in p.muxed_cells:
 116             bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
 117
 118         bsv_file.write("\n      endinterface\n")
 119
 120         bsv_file.write('''
 121
 122       interface IOCellSide;
 123       // declare the interface to the IO cells.
 124       // Each IO cell will have 1 input field (output from pin mux)
 125       // and an output and out-enable field (input to pinmux)''')
 126
 127         # == create method definitions for all iocell interfaces ==#
 128         iocells.ifacefmt(bsv_file)
 129
 130         # ===== finish interface definition and start module definition=======
 131         bsv_file.write("\n      endinterface\n")
 132
 133         # ===== io cell definition =======
 134         bsv_file.write('''
 135
 136       interface PeripheralSide;
 137       // declare the interface to the peripherals
 138       // Each peripheral's function will be either an input, output
 139       // or be bi-directional.  an input field will be an output from the
 140       // peripheral and an output field will be an input to the peripheral.
 141       // Bi-directional functions also have an output-enable (which
 142       // again comes *in* from the peripheral)''')
 143         # ==============================================================
 144
 145         # == create method definitions for all peripheral interfaces ==#
 146         ifaces.ifacefmt(bsv_file)
 147         bsv_file.write("\n      endinterface\n")
 148
 149         # ===== finish interface definition and start module definition=======
 150         bsv_file.write('''
 151
 152    interface Ifc_pinmux;
 153       // this interface controls how each IO cell is routed.  setting
 154       // any given IO cell's mux control value will result in redirection
 155       // of not just the input or output to different peripheral functions
 156       // but also the *direction* control - if appropriate - as well.
 157       interface MuxSelectionLines mux_lines;
 158
 159       // this interface contains the inputs, outputs and direction-control
 160       // lines for all peripherals.  GPIO is considered to also be just
 161       // a peripheral because it also has in, out and direction-control.
 162       interface PeripheralSide peripheral_side;
 163
 164       // this interface is to be linked to the individual IO cells.
 165       // if looking at a "non-muxed" GPIO design, basically the
 166       // IO cell input, output and direction-control wires are cut
 167       // (giving six pairs of dangling wires, named left and right)
 168       // these iocells are routed in their place on one side ("left")
 169       // and the matching *GPIO* peripheral interfaces in/out/dir
 170       // connect to the OTHER side ("right").  the result is that
 171       // the muxer settings end up controlling the routing of where
 172       // the I/O from the IOcell actually goes.
 173       interface IOCellSide iocell_side;
 174    endinterface
 175    (*synthesize*)
 176    module mkpinmux(Ifc_pinmux);
 177 ''')
 178         # ====================================================================
 179
 180         # ======================= create wire and registers =================#
 181         bsv_file.write('''
 182       // the followins wires capture the pin-mux selection
 183       // values for each mux assigned to a CELL
 184 ''')
 185         for cell in p.muxed_cells:
 186             bsv_file.write(mux_interface.wirefmt(
 187                 cell[0], cell_bit_width))
 188
 189         iocells.wirefmt(bsv_file)
 190         ifaces.wirefmt(bsv_file)
 191
 192         bsv_file.write("\n")
 193         # ====================================================================
 194         # ========================= Actual pinmuxing ========================#
 195         bsv_file.write('''
 196       /*====== This where the muxing starts for each io-cell======*/
 197       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 198 ''')
 199         bsv_file.write(p.pinmux)
 200         bsv_file.write('''
 201       /*============================================================*/
 202 ''')
 203         # ====================================================================
 204         # ================= interface definitions for each method =============#
 205         bsv_file.write('''
 206     interface mux_lines = interface MuxSelectionLines
 207 ''')
 208         for cell in p.muxed_cells:
 209             bsv_file.write(
 210                 mux_interface.ifacedef(
 211                     cell[0], cell_bit_width))
 212         bsv_file.write("\n    endinterface;")
 213
 214         bsv_file.write('''
 215     interface iocell_side = interface IOCellSide
 216 ''')
 217         iocells.ifacedef(bsv_file)
 218         bsv_file.write("\n     endinterface;")
 219
 220         bsv_file.write('''
 221     interface peripheral_side = interface PeripheralSide
 222 ''')
 223         ifaces.ifacedef(bsv_file)
 224         bsv_file.write("\n     endinterface;")
 225
 226         bsv_file.write(footer)
 227         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 228         # ======================================================================
 229
 230
 231 def write_ptp(ptp, p, ifaces):
 232     with open(ptp, 'w') as bsv_file:
 233         bsv_file.write(copyright + '''
 234 package PinTop;
 235     import pinmux::*;
 236     interface Ifc_PintTop;
 237         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 238         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 239         interface PeripheralSide peripheral_side;
 240     endinterface
 241
 242     module mkPinTop(Ifc_PintTop);
 243         // instantiate the pin-mux module here
 244         Ifc_pinmux pinmux <-mkpinmux;
 245
 246         // declare the registers which will be used to mux the IOs
 247 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 248
 249         cell_bit_width = str(p.cell_bitwidth)
 250         for cell in p.muxed_cells:
 251             bsv_file.write('''
 252                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 253                 cell_bit_width, cell[0]))
 254
 255         bsv_file.write('''
 256         // rule to connect the registers to the selection lines of the
 257         // pin-mux module
 258         rule connect_selection_registers;''')
 259
 260         for cell in p.muxed_cells:
 261             bsv_file.write('''
 262           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 263
 264         bsv_file.write('''
 265         endrule
 266         // method definitions for the write user interface
 267         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 268           Bool err=False;
 269           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 270                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 271         index = 0
 272         for cell in p.muxed_cells:
 273             bsv_file.write('''
 274             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 275             index = index + 1
 276
 277         bsv_file.write('''
 278             default: err=True;
 279           endcase
 280           return err;
 281         endmethod''')
 282
 283         bsv_file.write('''
 284         // method definitions for the read user interface
 285         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 286           Bool err=False;
 287           Bit#(32) data=0;
 288           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 289                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 290         index = 0
 291         for cell in p.muxed_cells:
 292             bsv_file.write('''
 293                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 294             index = index + 1
 295
 296         bsv_file.write('''
 297             default:err=True;
 298           endcase
 299           return tuple2(err,data);
 300         endmethod
 301         interface peripheral_side=pinmux.peripheral_side;
 302     endmodule
 303 endpackage
 304 ''')
 305
 306
 307 def write_bvp(bvp, p, ifaces):
 308     # ######## Generate bus transactors ################
 309     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 310               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 311     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 312         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 313
 314     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 315     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 316     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 317               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 318     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 319         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 320     with open(bvp, 'w') as bsv_file:
 321         # assume here that all muxes have a 1:1 gpio
 322         cfg = []
 323         decl = []
 324         idec = []
 325         iks = sorted(ifaces.keys())
 326         for iname in iks:
 327             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 328                 continue
 329             bank = iname[4:]
 330             ifc = ifaces[iname]
 331             npins = len(ifc.pinspecs)
 332             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 333                                       0,  # USERSPACE
 334                                       bank, npins))
 335             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 336                                      0,  # USERSPACE
 337                                      bank, npins))
 338             decl.append(gpiodec.format(npins, bank))
 339             decl.append(muxdec .format(npins, bank))
 340             idec.append(gpioifc.format(bank))
 341             idec.append(muxifc.format(bank))
 342         print dir(ifaces)
 343         print ifaces.items()
 344         print dir(ifaces['gpioa'])
 345         print ifaces['gpioa'].pinspecs
 346         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 347         gpiocfg = '\n'.join(cfg)
 348         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 349     # ##################################################
 350
 351 def write_instances(idef,  p, ifaces):
 352     with open(idef, 'w') as bsv_file:
 353         txt = '''\
 354     `define ADDR {0}
 355     `define DATA {1}
 356     `define USERSPACE 0
 357 '''
 358         bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH))