src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 '''
  43 footer = '''
  44    endmodule
  45 endpackage
  46 '''
  47
  48
  49 def pinmuxgen(pth=None, verify=True):
  50     """ populating the file with the code
  51     """
  52
  53     p = Parse(pth, verify)
  54     iocells = Interfaces()
  55     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  56     ifaces = Interfaces(pth)
  57     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  58     init(p, ifaces)
  59
  60     bp = 'bsv_src'
  61     if pth:
  62         bp = os.path.join(pth, bp)
  63     if not os.path.exists(bp):
  64         os.makedirs(bp)
  65     bl = os.path.join(bp, 'bsv_lib')
  66     if not os.path.exists(bl):
  67         os.makedirs(bl)
  68
  69     cwd = os.path.split(__file__)[0]
  70
  71     # copy over template and library files
  72     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  73                     os.path.join(bp, 'Makefile'))
  74     cwd = os.path.join(cwd, 'bsv_lib')
  75     for fname in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv',
  76                   'gpio.bsv', 'mux.bsv',
  77                   'AXI4_Types.bsv', 'defined_types.bsv',
  78                   'AXI4_Fabric.bsv', 'Uart16550.bsv',
  79                   'Uart_bs.bsv', 'RS232_modified.bsv',
  80                   'AXI4Lite_AXI4_Bridge.bsv',
  81                   'I2C_top.bsv', 'I2C_Defs.bsv',
  82                   'plic.bsv', 'Cur_Cycle.bsv',
  83                   'ClockDiv.bsv', 'axi_addr_generator.bsv',
  84                   'pwm.bsv', 'qspi.bsv', 'qspi.defs',
  85                   ]:
  86         shutil.copyfile(os.path.join(cwd, fname),
  87                         os.path.join(bl, fname))
  88
  89     bus = os.path.join(bp, 'busenable.bsv')
  90     pmp = os.path.join(bp, 'pinmux.bsv')
  91     ptp = os.path.join(bp, 'PinTop.bsv')
  92     bvp = os.path.join(bp, 'bus.bsv')
  93     idef = os.path.join(bp, 'instance_defines.bsv')
  94     slow = os.path.join(bp, 'slow_peripherals.bsv')
  95     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
  96
  97     write_pmp(pmp, p, ifaces, iocells)
  98     write_ptp(ptp, p, ifaces)
  99     write_bvp(bvp, p, ifaces)
 100     write_bus(bus, p, ifaces)
 101     write_instances(idef, p, ifaces)
 102     write_slow(slow, slowt, p, ifaces, iocells)
 103
 104
 105 def write_slow(slow, template, p, ifaces, iocells):
 106     """ write out the slow_peripherals.bsv file.
 107         joins all the peripherals together into one AXI Lite interface
 108     """
 109     with open(template) as bsv_file:
 110         template = bsv_file.read()
 111     imports = ifaces.slowimport()
 112     ifdecl = ifaces.slowifdecl()
 113     regdef = ifaces.axi_reg_def()
 114     slavedecl = ifaces.axi_slave_idx()
 115     fnaddrmap = ifaces.axi_addr_map()
 116     mkslow = ifaces.mkslow_peripheral()
 117     mkcon = ifaces.mk_connection()
 118     mkcellcon = ifaces.mk_cellconn()
 119     pincon = ifaces.mk_pincon()
 120     with open(slow, "w") as bsv_file:
 121         bsv_file.write(template.format(imports, ifdecl, regdef, slavedecl,
 122                                        fnaddrmap, mkslow, mkcon, mkcellcon,
 123                                        pincon))
 124
 125
 126 def write_bus(bus, p, ifaces):
 127     # package and interface declaration followed by
 128     # the generic io_cell definition
 129     with open(bus, "w") as bsv_file:
 130         ifaces.busfmt(bsv_file)
 131
 132
 133 def write_pmp(pmp, p, ifaces, iocells):
 134     # package and interface declaration followed by
 135     # the generic io_cell definition
 136     with open(pmp, "w") as bsv_file:
 137         bsv_file.write(header)
 138
 139         cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
 140         bsv_file.write('''\
 141    interface MuxSelectionLines;
 142
 143       // declare the method which will capture the user pin-mux
 144       // selection values.The width of the input is dependent on the number
 145       // of muxes happening per IO. For now we have a generalized width
 146       // where each IO will have the same number of muxes.''')
 147
 148         for cell in p.muxed_cells:
 149             bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
 150
 151         bsv_file.write("\n      endinterface\n")
 152
 153         bsv_file.write('''
 154
 155       interface IOCellSide;
 156       // declare the interface to the IO cells.
 157       // Each IO cell will have 1 input field (output from pin mux)
 158       // and an output and out-enable field (input to pinmux)''')
 159
 160         # == create method definitions for all iocell interfaces ==#
 161         iocells.ifacefmt(bsv_file)
 162
 163         # ===== finish interface definition and start module definition=======
 164         bsv_file.write("\n      endinterface\n")
 165
 166         # ===== io cell definition =======
 167         bsv_file.write('''
 168
 169       interface PeripheralSide;
 170       // declare the interface to the peripherals
 171       // Each peripheral's function will be either an input, output
 172       // or be bi-directional.  an input field will be an output from the
 173       // peripheral and an output field will be an input to the peripheral.
 174       // Bi-directional functions also have an output-enable (which
 175       // again comes *in* from the peripheral)''')
 176         # ==============================================================
 177
 178         # == create method definitions for all peripheral interfaces ==#
 179         ifaces.ifacefmt(bsv_file)
 180         bsv_file.write("\n      endinterface\n")
 181
 182         # ===== finish interface definition and start module definition=======
 183         bsv_file.write('''
 184
 185    interface Ifc_pinmux;
 186       // this interface controls how each IO cell is routed.  setting
 187       // any given IO cell's mux control value will result in redirection
 188       // of not just the input or output to different peripheral functions
 189       // but also the *direction* control - if appropriate - as well.
 190       interface MuxSelectionLines mux_lines;
 191
 192       // this interface contains the inputs, outputs and direction-control
 193       // lines for all peripherals.  GPIO is considered to also be just
 194       // a peripheral because it also has in, out and direction-control.
 195       interface PeripheralSide peripheral_side;
 196
 197       // this interface is to be linked to the individual IO cells.
 198       // if looking at a "non-muxed" GPIO design, basically the
 199       // IO cell input, output and direction-control wires are cut
 200       // (giving six pairs of dangling wires, named left and right)
 201       // these iocells are routed in their place on one side ("left")
 202       // and the matching *GPIO* peripheral interfaces in/out/dir
 203       // connect to the OTHER side ("right").  the result is that
 204       // the muxer settings end up controlling the routing of where
 205       // the I/O from the IOcell actually goes.
 206       interface IOCellSide iocell_side;
 207    endinterface
 208    (*synthesize*)
 209    module mkpinmux(Ifc_pinmux);
 210 ''')
 211         # ====================================================================
 212
 213         # ======================= create wire and registers =================#
 214         bsv_file.write('''
 215       // the followins wires capture the pin-mux selection
 216       // values for each mux assigned to a CELL
 217 ''')
 218         for cell in p.muxed_cells:
 219             bsv_file.write(mux_interface.wirefmt(
 220                 cell[0], cell_bit_width))
 221
 222         iocells.wirefmt(bsv_file)
 223         ifaces.wirefmt(bsv_file)
 224
 225         bsv_file.write("\n")
 226         # ====================================================================
 227         # ========================= Actual pinmuxing ========================#
 228         bsv_file.write('''
 229       /*====== This where the muxing starts for each io-cell======*/
 230       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 231 ''')
 232         bsv_file.write(p.pinmux)
 233         bsv_file.write('''
 234       /*============================================================*/
 235 ''')
 236         # ====================================================================
 237         # ================= interface definitions for each method =============#
 238         bsv_file.write('''
 239     interface mux_lines = interface MuxSelectionLines
 240 ''')
 241         for cell in p.muxed_cells:
 242             bsv_file.write(
 243                 mux_interface.ifacedef(
 244                     cell[0], cell_bit_width))
 245         bsv_file.write("\n    endinterface;")
 246
 247         bsv_file.write('''
 248     interface iocell_side = interface IOCellSide
 249 ''')
 250         iocells.ifacedef(bsv_file)
 251         bsv_file.write("\n     endinterface;")
 252
 253         bsv_file.write('''
 254     interface peripheral_side = interface PeripheralSide
 255 ''')
 256         ifaces.ifacedef(bsv_file)
 257         bsv_file.write("\n     endinterface;")
 258
 259         bsv_file.write(footer)
 260         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 261         # ======================================================================
 262
 263
 264 def write_ptp(ptp, p, ifaces):
 265     with open(ptp, 'w') as bsv_file:
 266         bsv_file.write(copyright + '''
 267 package PinTop;
 268     import pinmux::*;
 269     interface Ifc_PintTop;
 270         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 271         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 272         interface PeripheralSide peripheral_side;
 273     endinterface
 274
 275     module mkPinTop(Ifc_PintTop);
 276         // instantiate the pin-mux module here
 277         Ifc_pinmux pinmux <-mkpinmux;
 278
 279         // declare the registers which will be used to mux the IOs
 280 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 281
 282         cell_bit_width = str(p.cell_bitwidth)
 283         for cell in p.muxed_cells:
 284             bsv_file.write('''
 285                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 286                 cell_bit_width, cell[0]))
 287
 288         bsv_file.write('''
 289         // rule to connect the registers to the selection lines of the
 290         // pin-mux module
 291         rule connect_selection_registers;''')
 292
 293         for cell in p.muxed_cells:
 294             bsv_file.write('''
 295           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 296
 297         bsv_file.write('''
 298         endrule
 299         // method definitions for the write user interface
 300         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 301           Bool err=False;
 302           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 303                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 304         index = 0
 305         for cell in p.muxed_cells:
 306             bsv_file.write('''
 307             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 308             index = index + 1
 309
 310         bsv_file.write('''
 311             default: err=True;
 312           endcase
 313           return err;
 314         endmethod''')
 315
 316         bsv_file.write('''
 317         // method definitions for the read user interface
 318         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 319           Bool err=False;
 320           Bit#(32) data=0;
 321           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 322                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 323         index = 0
 324         for cell in p.muxed_cells:
 325             bsv_file.write('''
 326                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 327             index = index + 1
 328
 329         bsv_file.write('''
 330             default:err=True;
 331           endcase
 332           return tuple2(err,data);
 333         endmethod
 334         interface peripheral_side=pinmux.peripheral_side;
 335     endmodule
 336 endpackage
 337 ''')
 338
 339
 340 def write_bvp(bvp, p, ifaces):
 341     # ######## Generate bus transactors ################
 342     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 343               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 344     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 345         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 346
 347     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 348     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 349     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 350               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 351     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 352         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 353     with open(bvp, 'w') as bsv_file:
 354         # assume here that all muxes have a 1:1 gpio
 355         cfg = []
 356         decl = []
 357         idec = []
 358         iks = sorted(ifaces.keys())
 359         for iname in iks:
 360             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 361                 continue
 362             bank = iname[4:]
 363             ifc = ifaces[iname]
 364             npins = len(ifc.pinspecs)
 365             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 366                                       0,  # USERSPACE
 367                                       bank, npins))
 368             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 369                                      0,  # USERSPACE
 370                                      bank, npins))
 371             decl.append(gpiodec.format(npins, bank))
 372             decl.append(muxdec .format(npins, bank))
 373             idec.append(gpioifc.format(bank))
 374             idec.append(muxifc.format(bank))
 375         print dir(ifaces)
 376         print ifaces.items()
 377         print dir(ifaces['gpioa'])
 378         print ifaces['gpioa'].pinspecs
 379         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 380         gpiocfg = '\n'.join(cfg)
 381         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 382     # ##################################################
 383
 384
 385 def write_instances(idef, p, ifaces):
 386     with open(idef, 'w') as bsv_file:
 387         txt = '''\
 388     `define ADDR {0}
 389     `define DATA {1}
 390     `define USERSPACE 0
 391 '''
 392         bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH))