src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 import GetPut::*;
  43 import Vector::*;
  44
  45 '''
  46 footer = '''
  47    endmodule
  48 endpackage
  49 '''
  50
  51
  52 def pinmuxgen(pth=None, verify=True):
  53     """ populating the file with the code
  54     """
  55
  56     p = Parse(pth, verify)
  57     iocells = Interfaces()
  58     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  59     ifaces = Interfaces(pth)
  60     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  61     init(p, ifaces)
  62
  63     bp = 'bsv_src'
  64     if pth:
  65         bp = os.path.join(pth, bp)
  66     if not os.path.exists(bp):
  67         os.makedirs(bp)
  68     bl = os.path.join(bp, 'bsv_lib')
  69     if not os.path.exists(bl):
  70         os.makedirs(bl)
  71
  72     cwd = os.path.split(__file__)[0]
  73
  74     # copy over template and library files
  75     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  76                     os.path.join(bp, 'Makefile'))
  77     cwd = os.path.join(cwd, 'bsv_lib')
  78     for fname in []:
  79         shutil.copyfile(os.path.join(cwd, fname),
  80                         os.path.join(bl, fname))
  81
  82     bus = os.path.join(bp, 'busenable.bsv')
  83     pmp = os.path.join(bp, 'pinmux.bsv')
  84     ptp = os.path.join(bp, 'PinTop.bsv')
  85     bvp = os.path.join(bp, 'bus.bsv')
  86     idef = os.path.join(bp, 'instance_defines.bsv')
  87     slow = os.path.join(bp, 'slow_peripherals.bsv')
  88     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
  89     soc = os.path.join(bp, 'soc.bsv')
  90     soct = os.path.join(cwd, 'soc_template.bsv')
  91
  92     write_pmp(pmp, p, ifaces, iocells)
  93     write_ptp(ptp, p, ifaces)
  94     write_bvp(bvp, p, ifaces)
  95     write_bus(bus, p, ifaces)
  96     write_instances(idef, p, ifaces)
  97     write_slow(slow, slowt, p, ifaces, iocells)
  98     write_soc(soc, soct, p, ifaces, iocells)
  99
 100
 101 def write_slow(slow, slowt, p, ifaces, iocells):
 102     """ write out the slow_peripherals.bsv file.
 103         joins all the peripherals together into one AXI Lite interface
 104     """
 105     with open(slowt) as bsv_file:
 106         slowt = bsv_file.read()
 107     imports = ifaces.slowimport()
 108     ifdecl = ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 109     regdef = ifaces.axi_reg_def()
 110     slavedecl = ifaces.axi_slave_idx()
 111     fnaddrmap = ifaces.axi_addr_map()
 112     mkslow = ifaces.mkslow_peripheral()
 113     mkcon = ifaces.mk_connection()
 114     mkcellcon = ifaces.mk_cellconn()
 115     pincon = ifaces.mk_pincon()
 116     inst = ifaces.extifinstance()
 117     mkplic = ifaces.mk_plic()
 118     numsloirqs = ifaces.mk_sloirqsdef()
 119     ifacedef = ifaces.mk_ext_ifacedef()
 120     ifacedef = ifaces.mk_ext_ifacedef()
 121     with open(slow, "w") as bsv_file:
 122         bsv_file.write(slowt.format(imports, ifdecl, regdef, slavedecl,
 123                                     fnaddrmap, mkslow, mkcon, mkcellcon,
 124                                     pincon, inst, mkplic,
 125                                     numsloirqs, ifacedef))
 126
 127 def write_soc(soc, soct, p, ifaces, iocells):
 128     """ write out the soc.bsv file.
 129         joins all the peripherals together as AXI Masters
 130     """
 131     ifaces.fastbusmode = True # side-effects... shouldn't really do this
 132     with open(soct) as bsv_file:
 133         soct = bsv_file.read()
 134     imports = ifaces.slowimport()
 135     ifdecl = "" #ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 136     regdef = ifaces.axi_reg_def()
 137     slavedecl = ifaces.axi_slave_idx()
 138     fnaddrmap = ifaces.axi_addr_map()
 139     mkfast = ifaces.mkfast_peripheral()
 140     mkcon = ifaces.mk_connection()
 141     mkcellcon = ifaces.mk_cellconn()
 142     pincon = ifaces.mk_pincon()
 143     inst = ifaces.extifinstance()
 144     mkplic = ifaces.mk_plic()
 145     numsloirqs = ifaces.mk_sloirqsdef()
 146     ifacedef = ifaces.mk_ext_ifacedef()
 147     ifacedef = ifaces.mk_ext_ifacedef()
 148     with open(soc, "w") as bsv_file:
 149         bsv_file.write(soct.format(imports, ifdecl, mkfast,
 150                             #'', '' #regdef, slavedecl,
 151                             #'', mkslow, #fnaddrmap, mkslow, mkcon, mkcellcon,
 152                             #pincon, inst, mkplic,
 153                             #numsloirqs, ifacedef))
 154                                   ))
 155
 156
 157 def write_bus(bus, p, ifaces):
 158     # package and interface declaration followed by
 159     # the generic io_cell definition
 160     with open(bus, "w") as bsv_file:
 161         ifaces.busfmt(bsv_file)
 162
 163
 164 def write_pmp(pmp, p, ifaces, iocells):
 165     # package and interface declaration followed by
 166     # the generic io_cell definition
 167     with open(pmp, "w") as bsv_file:
 168         bsv_file.write(header)
 169
 170         cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
 171         bsv_file.write('''\
 172       (*always_ready,always_enabled*)
 173       interface MuxSelectionLines;
 174
 175       // declare the method which will capture the user pin-mux
 176       // selection values.The width of the input is dependent on the number
 177       // of muxes happening per IO. For now we have a generalized width
 178       // where each IO will have the same number of muxes.''')
 179
 180         for cell in p.muxed_cells:
 181             bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
 182
 183         bsv_file.write("\n      endinterface\n")
 184
 185         bsv_file.write('''
 186
 187       interface IOCellSide;
 188       // declare the interface to the IO cells.
 189       // Each IO cell will have 1 input field (output from pin mux)
 190       // and an output and out-enable field (input to pinmux)''')
 191
 192         # == create method definitions for all iocell interfaces ==#
 193         iocells.ifacefmt(bsv_file)
 194
 195         # ===== finish interface definition and start module definition=======
 196         bsv_file.write("\n      endinterface\n")
 197
 198         ifaces.ifacepfmt(bsv_file)
 199         # ===== io cell definition =======
 200         bsv_file.write('''
 201       (*always_ready,always_enabled*)
 202       interface PeripheralSide;
 203       // declare the interface to the peripherals
 204       // Each peripheral's function will be either an input, output
 205       // or be bi-directional.  an input field will be an output from the
 206       // peripheral and an output field will be an input to the peripheral.
 207       // Bi-directional functions also have an output-enable (which
 208       // again comes *in* from the peripheral)''')
 209         # ==============================================================
 210
 211         # == create method definitions for all peripheral interfaces ==#
 212         ifaces.ifacefmt2(bsv_file)
 213         bsv_file.write("\n      endinterface\n")
 214
 215         # ===== finish interface definition and start module definition=======
 216         bsv_file.write('''
 217
 218    interface Ifc_pinmux;
 219       // this interface controls how each IO cell is routed.  setting
 220       // any given IO cell's mux control value will result in redirection
 221       // of not just the input or output to different peripheral functions
 222       // but also the *direction* control - if appropriate - as well.
 223       interface MuxSelectionLines mux_lines;
 224
 225       // this interface contains the inputs, outputs and direction-control
 226       // lines for all peripherals.  GPIO is considered to also be just
 227       // a peripheral because it also has in, out and direction-control.
 228       interface PeripheralSide peripheral_side;
 229
 230       // this interface is to be linked to the individual IO cells.
 231       // if looking at a "non-muxed" GPIO design, basically the
 232       // IO cell input, output and direction-control wires are cut
 233       // (giving six pairs of dangling wires, named left and right)
 234       // these iocells are routed in their place on one side ("left")
 235       // and the matching *GPIO* peripheral interfaces in/out/dir
 236       // connect to the OTHER side ("right").  the result is that
 237       // the muxer settings end up controlling the routing of where
 238       // the I/O from the IOcell actually goes.
 239       interface IOCellSide iocell_side;
 240    endinterface
 241
 242    (*synthesize*)
 243    module mkpinmux(Ifc_pinmux);
 244 ''')
 245         # ====================================================================
 246
 247         # ======================= create wire and registers =================#
 248         bsv_file.write('''
 249       // the followins wires capture the pin-mux selection
 250       // values for each mux assigned to a CELL
 251 ''')
 252         for cell in p.muxed_cells:
 253             bsv_file.write(mux_interface.wirefmt(
 254                 cell[0], cell_bit_width))
 255
 256         iocells.wirefmt(bsv_file)
 257         ifaces.wirefmt(bsv_file)
 258
 259         bsv_file.write("\n")
 260         # ====================================================================
 261         # ========================= Actual pinmuxing ========================#
 262         bsv_file.write('''
 263       /*====== This where the muxing starts for each io-cell======*/
 264       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 265 ''')
 266         bsv_file.write(p.pinmux)
 267         bsv_file.write('''
 268       /*============================================================*/
 269 ''')
 270         # ====================================================================
 271         # ================= interface definitions for each method =============#
 272         bsv_file.write('''
 273     interface mux_lines = interface MuxSelectionLines
 274 ''')
 275         for cell in p.muxed_cells:
 276             bsv_file.write(
 277                 mux_interface.ifacedef(
 278                     cell[0], cell_bit_width))
 279         bsv_file.write("\n    endinterface;")
 280
 281         bsv_file.write('''
 282
 283     interface iocell_side = interface IOCellSide
 284 ''')
 285         iocells.ifacedef(bsv_file)
 286         bsv_file.write("\n     endinterface;")
 287
 288         bsv_file.write('''
 289
 290      interface peripheral_side = interface PeripheralSide
 291 ''')
 292         ifaces.ifacedef2(bsv_file)
 293         bsv_file.write("\n      endinterface;")
 294
 295         bsv_file.write(footer)
 296         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 297         # ======================================================================
 298
 299
 300 def write_ptp(ptp, p, ifaces):
 301     with open(ptp, 'w') as bsv_file:
 302         bsv_file.write(copyright + '''
 303 package PinTop;
 304     import pinmux::*;
 305     interface Ifc_PintTop;
 306         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 307         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 308         interface PeripheralSide peripheral_side;
 309     endinterface
 310
 311     module mkPinTop(Ifc_PintTop);
 312         // instantiate the pin-mux module here
 313         Ifc_pinmux pinmux <-mkpinmux;
 314
 315         // declare the registers which will be used to mux the IOs
 316 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 317
 318         cell_bit_width = str(p.cell_bitwidth)
 319         for cell in p.muxed_cells:
 320             bsv_file.write('''
 321                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 322                 cell_bit_width, cell[0]))
 323
 324         bsv_file.write('''
 325         // rule to connect the registers to the selection lines of the
 326         // pin-mux module
 327         rule connect_selection_registers;''')
 328
 329         for cell in p.muxed_cells:
 330             bsv_file.write('''
 331           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 332
 333         bsv_file.write('''
 334         endrule
 335         // method definitions for the write user interface
 336         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 337           Bool err=False;
 338           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 339                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 340         index = 0
 341         for cell in p.muxed_cells:
 342             bsv_file.write('''
 343             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 344             index = index + 1
 345
 346         bsv_file.write('''
 347             default: err=True;
 348           endcase
 349           return err;
 350         endmethod''')
 351
 352         bsv_file.write('''
 353         // method definitions for the read user interface
 354         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 355           Bool err=False;
 356           Bit#(32) data=0;
 357           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 358                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 359         index = 0
 360         for cell in p.muxed_cells:
 361             bsv_file.write('''
 362                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 363             index = index + 1
 364
 365         bsv_file.write('''
 366             default:err=True;
 367           endcase
 368           return tuple2(err,data);
 369         endmethod
 370         interface peripheral_side=pinmux.peripheral_side;
 371     endmodule
 372 endpackage
 373 ''')
 374
 375
 376 def write_bvp(bvp, p, ifaces):
 377     # ######## Generate bus transactors ################
 378     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 379               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 380     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 381         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 382
 383     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 384     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 385     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 386               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 387     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 388         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 389     with open(bvp, 'w') as bsv_file:
 390         # assume here that all muxes have a 1:1 gpio
 391         cfg = []
 392         decl = []
 393         idec = []
 394         iks = sorted(ifaces.keys())
 395         for iname in iks:
 396             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 397                 continue
 398             bank = iname[4:]
 399             ifc = ifaces[iname]
 400             npins = len(ifc.pinspecs)
 401             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 402                                       0,  # USERSPACE
 403                                       bank, npins))
 404             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 405                                      0,  # USERSPACE
 406                                      bank, npins))
 407             decl.append(gpiodec.format(npins, bank))
 408             decl.append(muxdec .format(npins, bank))
 409             idec.append(gpioifc.format(bank))
 410             idec.append(muxifc.format(bank))
 411         print dir(ifaces)
 412         print ifaces.items()
 413         print dir(ifaces['gpioa'])
 414         print ifaces['gpioa'].pinspecs
 415         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 416         gpiocfg = '\n'.join(cfg)
 417         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 418     # ##################################################
 419
 420
 421 def write_instances(idef, p, ifaces):
 422     with open(idef, 'w') as bsv_file:
 423         txt = '''\
 424 `define ADDR {0}
 425 `define PADDR {0}
 426 `define DATA {1}
 427 `define Reg_width {1}
 428 `define USERSPACE 0
 429
 430 // TODO: work out if these are needed
 431 `define PWM_AXI4Lite
 432 `define PRFDEPTH 6
 433 `define VADDR 39
 434 `define DCACHE_BLOCK_SIZE 4
 435 `define DCACHE_WORD_SIZE 8
 436 `define PERFMONITORS                            64
 437 `define DCACHE_WAYS 4
 438 `define DCACHE_TAG_BITS 20      // tag_bits = 52
 439 `define PLIC
 440         `define PLICBase                'h0c000000
 441         `define PLICEnd         'h10000000
 442 `define INTERRUPT_PINS 64
 443
 444 `define BAUD_RATE 130
 445 `ifdef simulate
 446   `define BAUD_RATE 5 //130 //
 447 `endif
 448 '''
 449         bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH))