src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import os
  20 import os.path
  21 import time
  22 import math
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42    typedef struct{
  43       Bit#(1) outputval;      // output from core to pad                bit7
  44       Bit#(1) output_en;      // output enable from core to pad         bit6
  45       Bit#(1) input_en;       // input enable from core to io_cell      bit5
  46       Bit#(1) pullup_en;      // pullup enable from core to io_cell     bit4
  47       Bit#(1) pulldown_en;    // pulldown enable from core to io_cell   bit3
  48       Bit#(1) drivestrength;  // drivestrength from core to io_cell     bit2
  49       Bit#(1) pushpull_en;    // pushpull enable from core to io_cell   bit1
  50       Bit#(1) opendrain_en;   // opendrain enable form core to io_cell  bit0
  51    } GenericIOType deriving(Eq,Bits,FShow);
  52
  53 '''
  54 footer = '''
  55      endinterface;
  56    endmodule
  57 endpackage
  58 '''
  59
  60
  61 def pinmuxgen(pth=None, verify=True):
  62     """ populating the file with the code
  63     """
  64
  65     p = Parse(pth, verify)
  66     ifaces = Interfaces(pth)
  67     ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  68     init(p, ifaces)
  69
  70     bp = 'bsv_src'
  71     if pth:
  72         bp = os.path.join(pth, bp)
  73     if not os.path.exists(bp):
  74         os.makedirs(bp)
  75
  76     bus = os.path.join(bp, 'busenable.bsv')
  77     pmp = os.path.join(bp, 'pinmux.bsv')
  78     ptp = os.path.join(bp, 'PinTop.bsv')
  79     bvp = os.path.join(bp, 'bus.bsv')
  80
  81     write_pmp(pmp, p, ifaces)
  82     write_ptp(ptp, p, ifaces)
  83     write_bvp(bvp, p, ifaces)
  84     write_bus(bus, p, ifaces)
  85
  86
  87 def write_bus(bus, p, ifaces):
  88     # package and interface declaration followed by
  89     # the generic io_cell definition
  90     with open(bus, "w") as bsv_file:
  91         ifaces.busfmt(bsv_file)
  92
  93
  94 def get_cell_bit_width(p):
  95     max_num_cells = 0
  96     for cell in p.muxed_cells:
  97             max_num_cells = max(len(cell)-1, max_num_cells)
  98     return int(math.log(max_num_cells, 2))
  99
 100 def write_pmp(pmp, p, ifaces):
 101     # package and interface declaration followed by
 102     # the generic io_cell definition
 103     with open(pmp, "w") as bsv_file:
 104         bsv_file.write(header)
 105
 106         bsv_file.write('''\
 107    interface MuxSelectionLines;
 108
 109       // declare the method which will capture the user pin-mux
 110       // selection values.The width of the input is dependent on the number
 111       // of muxes happening per IO. For now we have a generalized width
 112       // where each IO will have the same number of muxes.''')
 113
 114         for cell in p.muxed_cells:
 115             cnum = 'Bit#(' + str(int(math.log(len(cell) - 1, 2))) + ')'
 116             bsv_file.write(mux_interface.ifacefmt(cell[0], cnum))
 117
 118         bsv_file.write('''
 119       endinterface
 120
 121       interface PeripheralSide;
 122       // declare the interface to the IO cells.
 123       // Each IO cell will have 8 input field (output from pin mux
 124       // and on output field (input to pinmux)''')
 125         # ==============================================================
 126
 127         # == create method definitions for all peripheral interfaces ==#
 128         ifaces.ifacefmt(bsv_file)
 129
 130         # ==============================================================
 131
 132         # ===== finish interface definition and start module definition=======
 133         bsv_file.write('''
 134    endinterface
 135
 136    interface Ifc_pinmux;
 137       interface MuxSelectionLines mux_lines;
 138       interface PeripheralSide peripheral_side;
 139    endinterface
 140    (*synthesize*)
 141    module mkpinmux(Ifc_pinmux);
 142 ''')
 143         # ====================================================================
 144
 145         # ======================= create wire and registers =================#
 146         bsv_file.write('''
 147       // the followins wires capture the pin-mux selection
 148       // values for each mux assigned to a CELL
 149 ''')
 150         cell_bit_width = 'Bit#(%d)' % get_cell_bit_width(p)
 151         for cell in p.muxed_cells:
 152             bsv_file.write(mux_interface.wirefmt(
 153                 cell[0], cell_bit_width))
 154
 155         ifaces.wirefmt(bsv_file)
 156
 157         bsv_file.write("\n")
 158         # ====================================================================
 159         # ========================= Actual pinmuxing ========================#
 160         bsv_file.write('''
 161       /*====== This where the muxing starts for each io-cell======*/
 162 ''')
 163         bsv_file.write(p.pinmux)
 164         bsv_file.write('''
 165       /*============================================================*/
 166 ''')
 167         # ====================================================================
 168         # ================= interface definitions for each method =============#
 169         bsv_file.write('''
 170     interface mux_lines = interface MuxSelectionLines
 171 ''')
 172         for cell in p.muxed_cells:
 173             bsv_file.write(
 174                 mux_interface.ifacedef(
 175                     cell[0], cell_bit_width))
 176         bsv_file.write('''
 177     endinterface;
 178     interface peripheral_side = interface PeripheralSide
 179 ''')
 180         ifaces.ifacedef(bsv_file)
 181         bsv_file.write(footer)
 182         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 183         # ======================================================================
 184
 185
 186 def write_ptp(ptp, p, ifaces):
 187     with open(ptp, 'w') as bsv_file:
 188         bsv_file.write(copyright + '''
 189 package PinTop;
 190     import pinmux::*;
 191     interface Ifc_PintTop;
 192         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 193         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 194         interface PeripheralSide peripheral_side;
 195     endinterface
 196
 197     module mkPinTop(Ifc_PintTop);
 198         // instantiate the pin-mux module here
 199         Ifc_pinmux pinmux <-mkpinmux;
 200
 201         // declare the registers which will be used to mux the IOs
 202 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 203
 204         cell_bit_width = str(get_cell_bit_width(p))
 205         for cell in p.muxed_cells:
 206             bsv_file.write('''
 207                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 208                 cell_bit_width, cell[0]))
 209
 210         bsv_file.write('''
 211         // rule to connect the registers to the selection lines of the
 212         // pin-mux module
 213         rule connect_selection_registers;''')
 214
 215         for cell in p.muxed_cells:
 216             bsv_file.write('''
 217           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 218
 219         bsv_file.write('''
 220         endrule
 221         // method definitions for the write user interface
 222         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 223           Bool err=False;
 224           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 225                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 226         index = 0
 227         for cell in p.muxed_cells:
 228             bsv_file.write('''
 229             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 230             index = index + 1
 231
 232         bsv_file.write('''
 233             default: err=True;
 234           endcase
 235           return err;
 236         endmethod''')
 237
 238         bsv_file.write('''
 239         // method definitions for the read user interface
 240         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 241           Bool err=False;
 242           Bit#(32) data=0;
 243           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 244                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 245         index = 0
 246         for cell in p.muxed_cells:
 247             bsv_file.write('''
 248                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 249             index = index + 1
 250
 251         bsv_file.write('''
 252             default:err=True;
 253           endcase
 254           return tuple2(err,data);
 255         endmethod
 256         interface peripheral_side=pinmux.peripheral_side;
 257     endmodule
 258 endpackage
 259 ''')
 260
 261
 262 def write_bvp(bvp, p, ifaces):
 263     # ######## Generate bus transactors ################
 264     with open(bvp, 'w') as bsv_file:
 265         bsv_file.write(axi4_lite.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 266     # ##################################################