src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 import GetPut::*;
  43 import Vector::*;
  44
  45 '''
  46 footer = '''
  47    endmodule
  48 endpackage
  49 '''
  50
  51
  52 def pinmuxgen(pth=None, verify=True):
  53     """ populating the file with the code
  54     """
  55
  56     p = Parse(pth, verify)
  57     iocells = Interfaces()
  58     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  59     ifaces = Interfaces(pth)
  60     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  61     init(p, ifaces)
  62
  63     bp = 'bsv_src'
  64     if pth:
  65         bp = os.path.join(pth, bp)
  66     if not os.path.exists(bp):
  67         os.makedirs(bp)
  68     bl = os.path.join(bp, 'bsv_lib')
  69     if not os.path.exists(bl):
  70         os.makedirs(bl)
  71
  72     cwd = os.path.split(__file__)[0]
  73
  74     # copy over template and library files
  75     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  76                     os.path.join(bp, 'Makefile'))
  77     cwd = os.path.join(cwd, 'bsv_lib')
  78     for fname in []:
  79         shutil.copyfile(os.path.join(cwd, fname),
  80                         os.path.join(bl, fname))
  81
  82     bus = os.path.join(bp, 'busenable.bsv')
  83     pmp = os.path.join(bp, 'pinmux.bsv')
  84     ptp = os.path.join(bp, 'PinTop.bsv')
  85     bvp = os.path.join(bp, 'bus.bsv')
  86     idef = os.path.join(bp, 'instance_defines.bsv')
  87     slow = os.path.join(bp, 'slow_peripherals.bsv')
  88     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
  89     slowmf = os.path.join(bp, 'slow_memory_map.bsv')
  90     slowmt = os.path.join(cwd, 'slow_tuple2_template.bsv')
  91     soc = os.path.join(bp, 'socgen.bsv')
  92     soct = os.path.join(cwd, 'soc_template.bsv')
  93
  94     write_pmp(pmp, p, ifaces, iocells)
  95     write_ptp(ptp, p, ifaces)
  96     write_bvp(bvp, p, ifaces)
  97     write_bus(bus, p, ifaces)
  98     write_instances(idef, p, ifaces)
  99     write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells)
 100     write_soc(soc, soct, p, ifaces, iocells)
 101
 102
 103 def write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells):
 104     """ write out the slow_peripherals.bsv file.
 105         joins all the peripherals together into one AXI Lite interface
 106     """
 107     with open(slowmt) as bsv_file:
 108         slowmt = bsv_file.read()
 109     with open(slowt) as bsv_file:
 110         slowt = bsv_file.read()
 111     imports = ifaces.slowimport()
 112     ifdecl = ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 113     regdef = ifaces.axi_reg_def()
 114     slavedecl = ifaces.axi_slave_idx()
 115     fnaddrmap = ifaces.axi_addr_map()
 116     mkslow = ifaces.mkslow_peripheral()
 117     mkcon = ifaces.mk_connection()
 118     mkcellcon = ifaces.mk_cellconn()
 119     pincon = ifaces.mk_pincon()
 120     inst = ifaces.extifinstance()
 121     inst2 = ifaces.extifinstance2()
 122     mkplic = ifaces.mk_plic()
 123     numsloirqs = ifaces.mk_sloirqsdef()
 124     ifacedef = ifaces.mk_ext_ifacedef()
 125     ifacedef = ifaces.mk_ext_ifacedef()
 126
 127     with open(slow, "w") as bsv_file:
 128         bsv_file.write(slowt.format(imports, ifdecl, regdef, slavedecl,
 129                                     fnaddrmap, mkslow, mkcon, mkcellcon,
 130                                     pincon, inst, mkplic,
 131                                     numsloirqs, ifacedef,
 132                                     inst2))
 133     with open(slowmf, "w") as bsv_file:
 134         bsv_file.write(slowmt.format(regdef, slavedecl, fnaddrmap))
 135
 136
 137 def write_soc(soc, soct, p, ifaces, iocells):
 138     """ write out the soc.bsv file.
 139         joins all the peripherals together as AXI Masters
 140     """
 141     ifaces.fastbusmode = True  # side-effects... shouldn't really do this
 142     with open(soct) as bsv_file:
 143         soct = bsv_file.read()
 144     imports = ifaces.slowimport()
 145     ifdecl = ifaces.fastifdecl()
 146 #ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 147     regdef = ifaces.axi_fastmem_def()
 148     slavedecl = ifaces.axi_fastslave_idx()
 149     mastdecl = ifaces.axi_master_idx()
 150     fnaddrmap = ifaces.axi_addr_map()
 151     mkfast = ifaces.mkfast_peripheral()
 152     mkcon = ifaces.mk_fast_connection()
 153     mkcellcon = ifaces.mk_cellconn()
 154     pincon = ifaces.mk_pincon()
 155     inst = ifaces.extfastifinstance()
 156     mkplic = ifaces.mk_plic()
 157     numsloirqs = ifaces.mk_sloirqsdef()
 158     ifacedef = ifaces.mk_ext_ifacedef()
 159     dma = ifaces.mk_dma_irq()
 160     num_dmachannels = ifaces.num_dmachannels()
 161     with open(soc, "w") as bsv_file:
 162         bsv_file.write(soct.format(imports, ifdecl, mkfast,
 163                                    slavedecl, mastdecl, mkcon,
 164                                    inst, dma, num_dmachannels,
 165                                    pincon, regdef, fnaddrmap,
 166                                    ))
 167
 168
 169 def write_bus(bus, p, ifaces):
 170     # package and interface declaration followed by
 171     # the generic io_cell definition
 172     with open(bus, "w") as bsv_file:
 173         ifaces.busfmt(bsv_file)
 174
 175
 176 def write_pmp(pmp, p, ifaces, iocells):
 177     # package and interface declaration followed by
 178     # the generic io_cell definition
 179     with open(pmp, "w") as bsv_file:
 180         bsv_file.write(header)
 181
 182         cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
 183         bsv_file.write('''\
 184       (*always_ready,always_enabled*)
 185       interface MuxSelectionLines;
 186
 187       // declare the method which will capture the user pin-mux
 188       // selection values.The width of the input is dependent on the number
 189       // of muxes happening per IO. For now we have a generalized width
 190       // where each IO will have the same number of muxes.''')
 191
 192         for cell in p.muxed_cells:
 193             bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
 194
 195         bsv_file.write("\n      endinterface\n")
 196
 197         bsv_file.write('''
 198
 199       interface IOCellSide;
 200       // declare the interface to the IO cells.
 201       // Each IO cell will have 1 input field (output from pin mux)
 202       // and an output and out-enable field (input to pinmux)''')
 203
 204         # == create method definitions for all iocell interfaces ==#
 205         iocells.ifacefmt(bsv_file)
 206
 207         # ===== finish interface definition and start module definition=======
 208         bsv_file.write("\n      endinterface\n")
 209
 210         ifaces.ifacepfmt(bsv_file)
 211         # ===== io cell definition =======
 212         bsv_file.write('''
 213       (*always_ready,always_enabled*)
 214       interface PeripheralSide;
 215       // declare the interface to the peripherals
 216       // Each peripheral's function will be either an input, output
 217       // or be bi-directional.  an input field will be an output from the
 218       // peripheral and an output field will be an input to the peripheral.
 219       // Bi-directional functions also have an output-enable (which
 220       // again comes *in* from the peripheral)''')
 221         # ==============================================================
 222
 223         # == create method definitions for all peripheral interfaces ==#
 224         ifaces.ifacefmt2(bsv_file)
 225         bsv_file.write("\n      endinterface\n")
 226
 227         # ===== finish interface definition and start module definition=======
 228         bsv_file.write('''
 229
 230    interface Ifc_pinmux;
 231       // this interface controls how each IO cell is routed.  setting
 232       // any given IO cell's mux control value will result in redirection
 233       // of not just the input or output to different peripheral functions
 234       // but also the *direction* control - if appropriate - as well.
 235       interface MuxSelectionLines mux_lines;
 236
 237       // this interface contains the inputs, outputs and direction-control
 238       // lines for all peripherals.  GPIO is considered to also be just
 239       // a peripheral because it also has in, out and direction-control.
 240       interface PeripheralSide peripheral_side;
 241
 242       // this interface is to be linked to the individual IO cells.
 243       // if looking at a "non-muxed" GPIO design, basically the
 244       // IO cell input, output and direction-control wires are cut
 245       // (giving six pairs of dangling wires, named left and right)
 246       // these iocells are routed in their place on one side ("left")
 247       // and the matching *GPIO* peripheral interfaces in/out/dir
 248       // connect to the OTHER side ("right").  the result is that
 249       // the muxer settings end up controlling the routing of where
 250       // the I/O from the IOcell actually goes.
 251       interface IOCellSide iocell_side;
 252    endinterface
 253
 254    (*synthesize*)
 255    module mkpinmux(Ifc_pinmux);
 256 ''')
 257         # ====================================================================
 258
 259         # ======================= create wire and registers =================#
 260         bsv_file.write('''
 261       // the followins wires capture the pin-mux selection
 262       // values for each mux assigned to a CELL
 263 ''')
 264         for cell in p.muxed_cells:
 265             bsv_file.write(mux_interface.wirefmt(
 266                 cell[0], cell_bit_width))
 267
 268         iocells.wirefmt(bsv_file)
 269         ifaces.wirefmt(bsv_file)
 270
 271         bsv_file.write("\n")
 272         # ====================================================================
 273         # ========================= Actual pinmuxing ========================#
 274         bsv_file.write('''
 275       /*====== This where the muxing starts for each io-cell======*/
 276       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 277 ''')
 278         bsv_file.write(p.pinmux)
 279         bsv_file.write('''
 280       /*============================================================*/
 281 ''')
 282         # ====================================================================
 283         # ================= interface definitions for each method =============#
 284         bsv_file.write('''
 285     interface mux_lines = interface MuxSelectionLines
 286 ''')
 287         for cell in p.muxed_cells:
 288             bsv_file.write(
 289                 mux_interface.ifacedef(
 290                     cell[0], cell_bit_width))
 291         bsv_file.write("\n    endinterface;")
 292
 293         bsv_file.write('''
 294
 295     interface iocell_side = interface IOCellSide
 296 ''')
 297         iocells.ifacedef(bsv_file)
 298         bsv_file.write("\n     endinterface;")
 299
 300         bsv_file.write('''
 301
 302      interface peripheral_side = interface PeripheralSide
 303 ''')
 304         ifaces.ifacedef2(bsv_file)
 305         bsv_file.write("\n      endinterface;")
 306
 307         bsv_file.write(footer)
 308         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 309         # ======================================================================
 310
 311
 312 def write_ptp(ptp, p, ifaces):
 313     with open(ptp, 'w') as bsv_file:
 314         bsv_file.write(copyright + '''
 315 package PinTop;
 316     import pinmux::*;
 317     interface Ifc_PintTop;
 318         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 319         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 320         interface PeripheralSide peripheral_side;
 321     endinterface
 322
 323     module mkPinTop(Ifc_PintTop);
 324         // instantiate the pin-mux module here
 325         Ifc_pinmux pinmux <-mkpinmux;
 326
 327         // declare the registers which will be used to mux the IOs
 328 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 329
 330         cell_bit_width = str(p.cell_bitwidth)
 331         for cell in p.muxed_cells:
 332             bsv_file.write('''
 333                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 334                 cell_bit_width, cell[0]))
 335
 336         bsv_file.write('''
 337         // rule to connect the registers to the selection lines of the
 338         // pin-mux module
 339         rule connect_selection_registers;''')
 340
 341         for cell in p.muxed_cells:
 342             bsv_file.write('''
 343           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 344
 345         bsv_file.write('''
 346         endrule
 347         // method definitions for the write user interface
 348         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 349           Bool err=False;
 350           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 351                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 352         index = 0
 353         for cell in p.muxed_cells:
 354             bsv_file.write('''
 355             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 356             index = index + 1
 357
 358         bsv_file.write('''
 359             default: err=True;
 360           endcase
 361           return err;
 362         endmethod''')
 363
 364         bsv_file.write('''
 365         // method definitions for the read user interface
 366         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 367           Bool err=False;
 368           Bit#(32) data=0;
 369           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 370                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 371         index = 0
 372         for cell in p.muxed_cells:
 373             bsv_file.write('''
 374                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 375             index = index + 1
 376
 377         bsv_file.write('''
 378             default:err=True;
 379           endcase
 380           return tuple2(err,data);
 381         endmethod
 382         interface peripheral_side=pinmux.peripheral_side;
 383     endmodule
 384 endpackage
 385 ''')
 386
 387
 388 def write_bvp(bvp, p, ifaces):
 389     # ######## Generate bus transactors ################
 390     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 391               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 392     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 393         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 394
 395     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 396     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 397     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 398               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 399     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 400         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 401     with open(bvp, 'w') as bsv_file:
 402         # assume here that all muxes have a 1:1 gpio
 403         cfg = []
 404         decl = []
 405         idec = []
 406         iks = sorted(ifaces.keys())
 407         for iname in iks:
 408             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 409                 continue
 410             bank = iname[4:]
 411             ifc = ifaces[iname]
 412             npins = len(ifc.pinspecs)
 413             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 414                                       0,  # USERSPACE
 415                                       bank, npins))
 416             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 417                                      0,  # USERSPACE
 418                                      bank, npins))
 419             decl.append(gpiodec.format(npins, bank))
 420             decl.append(muxdec .format(npins, bank))
 421             idec.append(gpioifc.format(bank))
 422             idec.append(muxifc.format(bank))
 423         print dir(ifaces)
 424         print ifaces.items()
 425         print dir(ifaces['gpioa'])
 426         print ifaces['gpioa'].pinspecs
 427         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 428         gpiocfg = '\n'.join(cfg)
 429         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 430     # ##################################################
 431
 432
 433 def write_instances(idef, p, ifaces):
 434     with open(idef, 'w') as bsv_file:
 435         txt = '''\
 436 `define ADDR {0}
 437 `define PADDR {0}
 438 `define DATA {1}
 439 `define Reg_width {1}
 440 `define USERSPACE 0
 441 `define RV64
 442
 443 // TODO: work out if these are needed
 444 `define PWM_AXI4Lite
 445 `define PRFDEPTH 6
 446 `define VADDR 39
 447 `define DCACHE_BLOCK_SIZE 4
 448 `define DCACHE_WORD_SIZE 8
 449 `define PERFMONITORS                            64
 450 `define DCACHE_WAYS 4
 451 `define DCACHE_TAG_BITS 20      // tag_bits = 52
 452
 453 // CLINT
 454     `define ClintBase       'h02000000
 455     `define ClintEnd        'h020BFFFF
 456
 457 `define PLIC
 458         `define PLICBase                'h0c000000
 459         `define PLICEnd         'h10000000
 460 `define INTERRUPT_PINS 64
 461
 462 `define BAUD_RATE 130
 463 `ifdef simulate
 464   `define BAUD_RATE 5 //130 //
 465 `endif
 466 '''
 467         bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH))