1 # ================================== Steps to add peripherals ============
2 # Step-1: create interface declaration for the peripheral to be added.
3 # Remember these are interfaces defined for the pinmux and hence
4 # will be opposite to those defined at the peripheral.
5 # For eg. the output TX from the UART will be input (method Action)
7 # These changes will have to be done in interface_decl.py
8 # Step-2 define the wires that will be required to transfer data from the
9 # peripheral interface to the IO cell and vice-versa. Create a
10 # mkDWire for each input/output between the peripheral and the
11 # pinmux. Also create an implicit wire of GenericIOType for each cell
12 # that can be connected to a each bit from the peripheral.
13 # These changes will have to be done in wire_def.py
14 # Step-3: create the definitions for each of the methods defined above.
15 # These changes will have to be done in interface_decl.py
16 # ========================================================================
18 # default module imports
24 # project module imports
25 from bsv
.interface_decl
import Interfaces
, mux_interface
, io_interface
26 from parse
import Parse
27 from bsv
.actual_pinmux
import init
28 from bsv
.bus_transactors
import axi4_lite
32 This BSV file has been generated by the PinMux tool available at:
33 https://bitbucket.org/casl/pinmux.
35 Authors: Neel Gala, Luke
36 Date of generation: ''' + time
.strftime("%c") + '''
39 header
= copyright
+ '''
43 Bit#(1) outputval; // output from core to pad bit7
44 Bit#(1) output_en; // output enable from core to pad bit6
45 Bit#(1) input_en; // input enable from core to io_cell bit5
46 Bit#(1) pullup_en; // pullup enable from core to io_cell bit4
47 Bit#(1) pulldown_en; // pulldown enable from core to io_cell bit3
48 Bit#(1) drivestrength; // drivestrength from core to io_cell bit2
49 Bit#(1) pushpull_en; // pushpull enable from core to io_cell bit1
50 Bit#(1) opendrain_en; // opendrain enable form core to io_cell bit0
51 } GenericIOType deriving(Eq,Bits,FShow);
61 def pinmuxgen(pth
=None, verify
=True):
62 """ populating the file with the code
65 p
= Parse(pth
, verify
)
66 ifaces
= Interfaces(pth
)
67 ifaces
.ifaceadd('io', p
.N_IO
, io_interface
, 0)
72 bp
= os
.path
.join(pth
, bp
)
73 if not os
.path
.exists(bp
):
76 bus
= os
.path
.join(bp
, 'busenable.bsv')
77 pmp
= os
.path
.join(bp
, 'pinmux.bsv')
78 ptp
= os
.path
.join(bp
, 'PinTop.bsv')
79 bvp
= os
.path
.join(bp
, 'bus.bsv')
81 write_pmp(pmp
, p
, ifaces
)
82 write_ptp(ptp
, p
, ifaces
)
83 write_bvp(bvp
, p
, ifaces
)
84 write_bus(bus
, p
, ifaces
)
87 def write_bus(bus
, p
, ifaces
):
88 # package and interface declaration followed by
89 # the generic io_cell definition
90 with
open(bus
, "w") as bsv_file
:
91 ifaces
.busfmt(bsv_file
)
94 def write_pmp(pmp
, p
, ifaces
):
95 # package and interface declaration followed by
96 # the generic io_cell definition
97 with
open(pmp
, "w") as bsv_file
:
98 bsv_file
.write(header
)
101 interface MuxSelectionLines;
103 // declare the method which will capture the user pin-mux
104 // selection values.The width of the input is dependent on the number
105 // of muxes happening per IO. For now we have a generalized width
106 // where each IO will have the same number of muxes.''')
108 for cell
in p
.muxed_cells
:
109 cnum
= 'Bit#(' + str(int(math
.log(len(cell
) - 1, 2))) + ')'
110 bsv_file
.write(mux_interface
.ifacefmt(cell
[0], cnum
))
115 interface PeripheralSide;
116 // declare the interface to the IO cells.
117 // Each IO cell will have 8 input field (output from pin mux
118 // and on output field (input to pinmux)''')
119 # ==============================================================
121 # == create method definitions for all peripheral interfaces ==#
122 ifaces
.ifacefmt(bsv_file
)
124 # ==============================================================
126 # ===== finish interface definition and start module definition=======
130 interface Ifc_pinmux;
131 interface MuxSelectionLines mux_lines;
132 interface PeripheralSide peripheral_side;
135 module mkpinmux(Ifc_pinmux);
137 # ====================================================================
139 # ======================= create wire and registers =================#
141 // the followins wires capture the pin-mux selection
142 // values for each mux assigned to a CELL
145 for cell
in p
.muxed_cells
:
146 max_num_cells
= max(len(cell
)-1, max_num_cells
)
147 cell_bit_width
= 'Bit#(%d)' %int
(math
.log(max_num_cells
, 2))
149 for cell
in p
.muxed_cells
:
150 bsv_file
.write(mux_interface
.wirefmt(
151 cell
[0], cell_bit_width
))
153 ifaces
.wirefmt(bsv_file
)
156 # ====================================================================
157 # ========================= Actual pinmuxing ========================#
159 /*====== This where the muxing starts for each io-cell======*/
161 bsv_file
.write(p
.pinmux
)
163 /*============================================================*/
165 # ====================================================================
166 # ================= interface definitions for each method =============#
168 interface mux_lines = interface MuxSelectionLines
170 for cell
in p
.muxed_cells
:
172 mux_interface
.ifacedef(
173 cell
[0], 'Bit#(' + str(int(
175 len(cell
) - 1, 2))) + ')'))
178 interface peripheral_side = interface PeripheralSide
180 ifaces
.ifacedef(bsv_file
)
181 bsv_file
.write(footer
)
182 print("BSV file successfully generated: bsv_src/pinmux.bsv")
183 # ======================================================================
186 def write_ptp(ptp
, p
, ifaces
):
187 with
open(ptp
, 'w') as bsv_file
:
188 bsv_file
.write(copyright
+ '''
191 interface Ifc_PintTop;
192 method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
193 method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
194 interface PeripheralSide peripheral_side;
197 module mkPinTop(Ifc_PintTop);
198 // instantiate the pin-mux module here
199 Ifc_pinmux pinmux <-mkpinmux;
201 // declare the registers which will be used to mux the IOs
202 '''.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
204 for cell
in p
.muxed_cells
:
206 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
207 int(math
.log(len(cell
) - 1, 2)), cell
[0]))
210 // rule to connect the registers to the selection lines of the
212 rule connect_selection_registers;''')
214 for cell
in p
.muxed_cells
:
216 pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell
[0]))
220 // method definitions for the write user interface
221 method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
223 case (addr[{0}:{1}])'''.format(p
.upper_offset
, p
.lower_offset
,
224 p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
226 for cell
in p
.muxed_cells
:
228 {0}: rg_muxio_{1}<=truncate(data);'''.format(index
, cell
[0]))
238 // method definitions for the read user interface
239 method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
242 case (addr[{0}:{1}])'''.format(p
.upper_offset
, p
.lower_offset
,
243 p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
245 for cell
in p
.muxed_cells
:
247 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index
, cell
[0]))
253 return tuple2(err,data);
255 interface peripheral_side=pinmux.peripheral_side;
261 def write_bvp(bvp
, p
, ifaces
):
262 # ######## Generate bus transactors ################
263 with
open(bvp
, 'w') as bsv_file
:
264 bsv_file
.write(axi4_lite
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
265 # ##################################################