1 # ================================== Steps to add peripherals ============
2 # Step-1: create interface declaration for the peripheral to be added.
3 # Remember these are interfaces defined for the pinmux and hence
4 # will be opposite to those defined at the peripheral.
5 # For eg. the output TX from the UART will be input (method Action)
7 # These changes will have to be done in interface_decl.py
8 # Step-2 define the wires that will be required to transfer data from the
9 # peripheral interface to the IO cell and vice-versa. Create a
10 # mkDWire for each input/output between the peripheral and the
11 # pinmux. Also create an implicit wire of GenericIOType for each cell
12 # that can be connected to a each bit from the peripheral.
13 # These changes will have to be done in wire_def.py
14 # Step-3: create the definitions for each of the methods defined above.
15 # These changes will have to be done in interface_decl.py
16 # ========================================================================
18 # default module imports
24 # project module imports
25 from bsv
.interface_decl
import Interfaces
, mux_interface
, io_interface
26 from parse
import Parse
27 from bsv
.actual_pinmux
import init
28 from bsv
.bus_transactors
import axi4_lite
32 This BSV file has been generated by the PinMux tool available at:
33 https://bitbucket.org/casl/pinmux.
35 Authors: Neel Gala, Luke
36 Date of generation: ''' + time
.strftime("%c") + '''
39 header
= copyright
+ '''
52 def pinmuxgen(pth
=None, verify
=True):
53 """ populating the file with the code
56 p
= Parse(pth
, verify
)
57 iocells
= Interfaces()
58 iocells
.ifaceadd('io', p
.N_IO
, io_interface
, 0)
59 ifaces
= Interfaces(pth
)
60 #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
65 bp
= os
.path
.join(pth
, bp
)
66 if not os
.path
.exists(bp
):
68 bl
= os
.path
.join(bp
, 'bsv_lib')
69 if not os
.path
.exists(bl
):
72 cwd
= os
.path
.split(__file__
)[0]
74 # copy over template and library files
75 shutil
.copyfile(os
.path
.join(cwd
, 'Makefile.template'),
76 os
.path
.join(bp
, 'Makefile'))
77 cwd
= os
.path
.join(cwd
, 'bsv_lib')
79 shutil
.copyfile(os
.path
.join(cwd
, fname
),
80 os
.path
.join(bl
, fname
))
82 bus
= os
.path
.join(bp
, 'busenable.bsv')
83 pmp
= os
.path
.join(bp
, 'pinmux.bsv')
84 ptp
= os
.path
.join(bp
, 'PinTop.bsv')
85 bvp
= os
.path
.join(bp
, 'bus.bsv')
86 idef
= os
.path
.join(bp
, 'instance_defines.bsv')
87 slow
= os
.path
.join(bp
, 'slow_peripherals.bsv')
88 slowt
= os
.path
.join(cwd
, 'slow_peripherals_template.bsv')
89 slowmf
= os
.path
.join(bp
, 'slow_memory_map.bsv')
90 slowmt
= os
.path
.join(cwd
, 'slow_tuple2_template.bsv')
91 fastmf
= os
.path
.join(bp
, 'fast_memory_map.bsv')
92 fastmt
= os
.path
.join(cwd
, 'fast_tuple2_template.bsv')
93 soc
= os
.path
.join(bp
, 'socgen.bsv')
94 soct
= os
.path
.join(cwd
, 'soc_template.bsv')
96 write_pmp(pmp
, p
, ifaces
, iocells
)
97 write_ptp(ptp
, p
, ifaces
)
98 write_bvp(bvp
, p
, ifaces
)
99 write_bus(bus
, p
, ifaces
)
100 write_instances(idef
, p
, ifaces
)
101 write_slow(slow
, slowt
, slowmf
, slowmt
, p
, ifaces
, iocells
)
102 write_soc(soc
, soct
, fastmf
, fastmt
, p
, ifaces
, iocells
)
105 def write_slow(slow
, slowt
, slowmf
, slowmt
, p
, ifaces
, iocells
):
106 """ write out the slow_peripherals.bsv file.
107 joins all the peripherals together into one AXI Lite interface
109 imports
= ifaces
.slowimport()
110 ifdecl
= ifaces
.slowifdeclmux() + '\n' + ifaces
.extifdecl()
111 regdef
= ifaces
.axi_reg_def()
112 slavedecl
= ifaces
.axi_slave_idx()
113 fnaddrmap
= ifaces
.axi_addr_map()
114 mkslow
= ifaces
.mkslow_peripheral()
115 mkcon
= ifaces
.mk_connection()
116 mkcellcon
= ifaces
.mk_cellconn()
117 pincon
= ifaces
.mk_pincon()
118 inst
= ifaces
.extifinstance()
119 inst2
= ifaces
.extifinstance2()
120 mkplic
= ifaces
.mk_plic()
121 numsloirqs
= ifaces
.mk_sloirqsdef()
122 ifacedef
= ifaces
.mk_ext_ifacedef()
123 ifacedef
= ifaces
.mk_ext_ifacedef()
124 clockcon
= ifaces
.mk_clk_con()
126 with
open(slow
, "w") as bsv_file
:
127 with
open(slowt
) as f
:
129 bsv_file
.write(slowt
.format(imports
, ifdecl
, regdef
, slavedecl
,
130 fnaddrmap
, mkslow
, mkcon
, mkcellcon
,
131 pincon
, inst
, mkplic
,
132 numsloirqs
, ifacedef
,
135 with
open(slowmf
, "w") as bsv_file
:
136 with
open(slowmt
) as f
:
138 bsv_file
.write(slowmt
.format(regdef
, slavedecl
, fnaddrmap
))
141 def write_soc(soc
, soct
, fastmf
, fastmt
, p
, ifaces
, iocells
):
142 """ write out the soc.bsv file.
143 joins all the peripherals together as AXI Masters
145 ifaces
.fastbusmode
= True # side-effects... shouldn't really do this
147 imports
= ifaces
.slowimport()
148 ifdecl
= ifaces
.fastifdecl()
149 regdef
= ifaces
.axi_fastmem_def()
150 slavedecl
= ifaces
.axi_fastslave_idx()
151 mastdecl
= ifaces
.axi_master_idx()
152 fnaddrmap
= ifaces
.axi_fastaddr_map()
153 mkfast
= ifaces
.mkfast_peripheral()
154 mkcon
= ifaces
.mk_fast_connection()
155 mkcellcon
= ifaces
.mk_cellconn()
156 pincon
= ifaces
.mk_fast_pincon()
157 inst
= ifaces
.extfastifinstance()
158 mkplic
= ifaces
.mk_plic()
159 numsloirqs
= ifaces
.mk_sloirqsdef()
160 ifacedef
= ifaces
.mk_ext_ifacedef()
161 dma
= ifaces
.mk_dma_irq()
162 num_dmachannels
= ifaces
.num_dmachannels()
164 with
open(soc
, "w") as bsv_file
:
165 with
open(soct
) as f
:
167 bsv_file
.write(soct
.format(imports
, ifdecl
, mkfast
,
168 slavedecl
, mastdecl
, mkcon
,
169 inst
, dma
, num_dmachannels
,
170 pincon
, regdef
, fnaddrmap
,
173 with
open(fastmf
, "w") as bsv_file
:
174 with
open(fastmt
) as f
:
176 bsv_file
.write(fastmt
.format(regdef
, slavedecl
, mastdecl
, fnaddrmap
))
179 def write_bus(bus
, p
, ifaces
):
180 # package and interface declaration followed by
181 # the generic io_cell definition
182 with
open(bus
, "w") as bsv_file
:
183 ifaces
.busfmt(bsv_file
)
186 def write_pmp(pmp
, p
, ifaces
, iocells
):
187 # package and interface declaration followed by
188 # the generic io_cell definition
189 with
open(pmp
, "w") as bsv_file
:
190 bsv_file
.write(header
)
192 cell_bit_width
= 'Bit#(%d)' % p
.cell_bitwidth
194 (*always_ready,always_enabled*)
195 interface MuxSelectionLines;
197 // declare the method which will capture the user pin-mux
198 // selection values.The width of the input is dependent on the number
199 // of muxes happening per IO. For now we have a generalized width
200 // where each IO will have the same number of muxes.''')
202 for cell
in p
.muxed_cells
:
203 bsv_file
.write(mux_interface
.ifacefmt(cell
[0], cell_bit_width
))
205 bsv_file
.write("\n endinterface\n")
209 interface IOCellSide;
210 // declare the interface to the IO cells.
211 // Each IO cell will have 1 input field (output from pin mux)
212 // and an output and out-enable field (input to pinmux)''')
214 # == create method definitions for all iocell interfaces ==#
215 iocells
.ifacefmt(bsv_file
)
217 # ===== finish interface definition and start module definition=======
218 bsv_file
.write("\n endinterface\n")
220 ifaces
.ifacepfmt(bsv_file
)
221 # ===== io cell definition =======
223 (*always_ready,always_enabled*)
224 interface PeripheralSide;
225 // declare the interface to the peripherals
226 // Each peripheral's function will be either an input, output
227 // or be bi-directional. an input field will be an output from the
228 // peripheral and an output field will be an input to the peripheral.
229 // Bi-directional functions also have an output-enable (which
230 // again comes *in* from the peripheral)''')
231 # ==============================================================
233 # == create method definitions for all peripheral interfaces ==#
234 ifaces
.ifacefmt2(bsv_file
)
235 bsv_file
.write("\n endinterface\n")
237 # ===== finish interface definition and start module definition=======
240 interface Ifc_pinmux;
241 // this interface controls how each IO cell is routed. setting
242 // any given IO cell's mux control value will result in redirection
243 // of not just the input or output to different peripheral functions
244 // but also the *direction* control - if appropriate - as well.
245 interface MuxSelectionLines mux_lines;
247 // this interface contains the inputs, outputs and direction-control
248 // lines for all peripherals. GPIO is considered to also be just
249 // a peripheral because it also has in, out and direction-control.
250 interface PeripheralSide peripheral_side;
252 // this interface is to be linked to the individual IO cells.
253 // if looking at a "non-muxed" GPIO design, basically the
254 // IO cell input, output and direction-control wires are cut
255 // (giving six pairs of dangling wires, named left and right)
256 // these iocells are routed in their place on one side ("left")
257 // and the matching *GPIO* peripheral interfaces in/out/dir
258 // connect to the OTHER side ("right"). the result is that
259 // the muxer settings end up controlling the routing of where
260 // the I/O from the IOcell actually goes.
261 interface IOCellSide iocell_side;
265 module mkpinmux(Ifc_pinmux);
267 # ====================================================================
269 # ======================= create wire and registers =================#
271 // the followins wires capture the pin-mux selection
272 // values for each mux assigned to a CELL
274 for cell
in p
.muxed_cells
:
275 bsv_file
.write(mux_interface
.wirefmt(
276 cell
[0], cell_bit_width
))
278 iocells
.wirefmt(bsv_file
)
279 ifaces
.wirefmt(bsv_file
)
282 # ====================================================================
283 # ========================= Actual pinmuxing ========================#
285 /*====== This where the muxing starts for each io-cell======*/
286 Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
288 bsv_file
.write(p
.pinmux
)
290 /*============================================================*/
292 # ====================================================================
293 # ================= interface definitions for each method =============#
295 interface mux_lines = interface MuxSelectionLines
297 for cell
in p
.muxed_cells
:
299 mux_interface
.ifacedef(
300 cell
[0], cell_bit_width
))
301 bsv_file
.write("\n endinterface;")
305 interface iocell_side = interface IOCellSide
307 iocells
.ifacedef(bsv_file
)
308 bsv_file
.write("\n endinterface;")
312 interface peripheral_side = interface PeripheralSide
314 ifaces
.ifacedef2(bsv_file
)
315 bsv_file
.write("\n endinterface;")
317 bsv_file
.write(footer
)
318 print("BSV file successfully generated: bsv_src/pinmux.bsv")
319 # ======================================================================
322 def write_ptp(ptp
, p
, ifaces
):
323 with
open(ptp
, 'w') as bsv_file
:
324 bsv_file
.write(copyright
+ '''
327 interface Ifc_PintTop;
328 method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
329 method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
330 interface PeripheralSide peripheral_side;
333 module mkPinTop(Ifc_PintTop);
334 // instantiate the pin-mux module here
335 Ifc_pinmux pinmux <-mkpinmux;
337 // declare the registers which will be used to mux the IOs
338 '''.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
340 cell_bit_width
= str(p
.cell_bitwidth
)
341 for cell
in p
.muxed_cells
:
343 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
344 cell_bit_width
, cell
[0]))
347 // rule to connect the registers to the selection lines of the
349 rule connect_selection_registers;''')
351 for cell
in p
.muxed_cells
:
353 pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell
[0]))
357 // method definitions for the write user interface
358 method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
360 case (addr[{0}:{1}])'''.format(p
.upper_offset
, p
.lower_offset
,
361 p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
363 for cell
in p
.muxed_cells
:
365 {0}: rg_muxio_{1}<=truncate(data);'''.format(index
, cell
[0]))
375 // method definitions for the read user interface
376 method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
379 case (addr[{0}:{1}])'''.format(p
.upper_offset
, p
.lower_offset
,
380 p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
382 for cell
in p
.muxed_cells
:
384 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index
, cell
[0]))
390 return tuple2(err,data);
392 interface peripheral_side=pinmux.peripheral_side;
398 def write_bvp(bvp
, p
, ifaces
):
399 # ######## Generate bus transactors ################
400 gpiocfg
= '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
401 '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
402 muxcfg
= '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
403 '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
405 gpiodec
= '\tGPIO#({0}) mygpio{1} <- mkgpio();'
406 muxdec
= '\tMUX#({0}) mymux{1} <- mkmux();'
407 gpioifc
= '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
408 '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
409 muxifc
= '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
410 '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
411 with
open(bvp
, 'w') as bsv_file
:
412 # assume here that all muxes have a 1:1 gpio
416 iks
= sorted(ifaces
.keys())
418 if not iname
.startswith('gpio'): # TODO: declare other interfaces
422 npins
= len(ifc
.pinspecs
)
423 cfg
.append(gpiocfg
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
,
426 cfg
.append(muxcfg
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
,
429 decl
.append(gpiodec
.format(npins
, bank
))
430 decl
.append(muxdec
.format(npins
, bank
))
431 idec
.append(gpioifc
.format(bank
))
432 idec
.append(muxifc
.format(bank
))
435 print dir(ifaces
['gpioa'])
436 print ifaces
['gpioa'].pinspecs
437 gpiodecl
= '\n'.join(decl
) + '\n' + '\n'.join(idec
)
438 gpiocfg
= '\n'.join(cfg
)
439 bsv_file
.write(axi4_lite
.format(gpiodecl
, gpiocfg
))
440 # ##################################################
443 def write_instances(idef
, p
, ifaces
):
444 with
open(idef
, 'w') as bsv_file
:
449 `define Reg_width {1}
453 // TODO: work out if these are needed
457 `define DCACHE_BLOCK_SIZE 4
458 `define DCACHE_WORD_SIZE 8
459 `define PERFMONITORS 64
460 `define DCACHE_WAYS 4
461 `define DCACHE_TAG_BITS 20 // tag_bits = 52
464 `define ClintBase 'h02000000
465 `define ClintEnd 'h020BFFFF
468 `define PLICBase 'h0c000000
469 `define PLICEnd 'h10000000
470 `define INTERRUPT_PINS 64
472 `define BAUD_RATE 130
474 `define BAUD_RATE 5 //130 //
477 bsv_file
.write(txt
.format(p
.ADDR_WIDTH
,