src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 import GetPut::*;
  43
  44 '''
  45 footer = '''
  46    endmodule
  47 endpackage
  48 '''
  49
  50
  51 def pinmuxgen(pth=None, verify=True):
  52     """ populating the file with the code
  53     """
  54
  55     p = Parse(pth, verify)
  56     iocells = Interfaces()
  57     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  58     ifaces = Interfaces(pth)
  59     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  60     init(p, ifaces)
  61
  62     bp = 'bsv_src'
  63     if pth:
  64         bp = os.path.join(pth, bp)
  65     if not os.path.exists(bp):
  66         os.makedirs(bp)
  67     bl = os.path.join(bp, 'bsv_lib')
  68     if not os.path.exists(bl):
  69         os.makedirs(bl)
  70
  71     cwd = os.path.split(__file__)[0]
  72
  73     # copy over template and library files
  74     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  75                     os.path.join(bp, 'Makefile'))
  76     cwd = os.path.join(cwd, 'bsv_lib')
  77     for fname in [ ]:
  78         shutil.copyfile(os.path.join(cwd, fname),
  79                         os.path.join(bl, fname))
  80
  81     bus = os.path.join(bp, 'busenable.bsv')
  82     pmp = os.path.join(bp, 'pinmux.bsv')
  83     ptp = os.path.join(bp, 'PinTop.bsv')
  84     bvp = os.path.join(bp, 'bus.bsv')
  85     idef = os.path.join(bp, 'instance_defines.bsv')
  86     slow = os.path.join(bp, 'slow_peripherals.bsv')
  87     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
  88
  89     write_pmp(pmp, p, ifaces, iocells)
  90     write_ptp(ptp, p, ifaces)
  91     write_bvp(bvp, p, ifaces)
  92     write_bus(bus, p, ifaces)
  93     write_instances(idef, p, ifaces)
  94     write_slow(slow, slowt, p, ifaces, iocells)
  95
  96
  97 def write_slow(slow, slowt, p, ifaces, iocells):
  98     """ write out the slow_peripherals.bsv file.
  99         joins all the peripherals together into one AXI Lite interface
 100     """
 101     with open(slowt) as bsv_file:
 102         slowt = bsv_file.read()
 103     imports = ifaces.slowimport()
 104     ifdecl = ifaces.slowifdeclmux()
 105     regdef = ifaces.axi_reg_def()
 106     slavedecl = ifaces.axi_slave_idx()
 107     fnaddrmap = ifaces.axi_addr_map()
 108     mkslow = ifaces.mkslow_peripheral()
 109     mkcon = ifaces.mk_connection()
 110     mkcellcon = ifaces.mk_cellconn()
 111     pincon = ifaces.mk_pincon()
 112     inst = ifaces.slowifinstance()
 113     mkplic = ifaces.mk_plic()
 114     numsloirqs = ifaces.mk_sloirqsdef()
 115     ifacedef = ifaces.mk_ext_ifacedef()
 116     ifacedef = ifaces.mk_ext_ifacedef()
 117     with open(slow, "w") as bsv_file:
 118         bsv_file.write(slowt.format(imports, ifdecl, regdef, slavedecl,
 119                                        fnaddrmap, mkslow, mkcon, mkcellcon,
 120                                        pincon, inst, mkplic,
 121                                        numsloirqs, ifacedef))
 122
 123
 124 def write_bus(bus, p, ifaces):
 125     # package and interface declaration followed by
 126     # the generic io_cell definition
 127     with open(bus, "w") as bsv_file:
 128         ifaces.busfmt(bsv_file)
 129
 130
 131 def write_pmp(pmp, p, ifaces, iocells):
 132     # package and interface declaration followed by
 133     # the generic io_cell definition
 134     with open(pmp, "w") as bsv_file:
 135         bsv_file.write(header)
 136
 137         cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
 138         bsv_file.write('''\
 139       (*always_ready,always_enabled*)
 140       interface MuxSelectionLines;
 141
 142       // declare the method which will capture the user pin-mux
 143       // selection values.The width of the input is dependent on the number
 144       // of muxes happening per IO. For now we have a generalized width
 145       // where each IO will have the same number of muxes.''')
 146
 147         for cell in p.muxed_cells:
 148             bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
 149
 150         bsv_file.write("\n      endinterface\n")
 151
 152         bsv_file.write('''
 153
 154       interface IOCellSide;
 155       // declare the interface to the IO cells.
 156       // Each IO cell will have 1 input field (output from pin mux)
 157       // and an output and out-enable field (input to pinmux)''')
 158
 159         # == create method definitions for all iocell interfaces ==#
 160         iocells.ifacefmt(bsv_file)
 161
 162         # ===== finish interface definition and start module definition=======
 163         bsv_file.write("\n      endinterface\n")
 164
 165         ifaces.ifacepfmt(bsv_file)
 166         # ===== io cell definition =======
 167         bsv_file.write('''
 168       (*always_ready,always_enabled*)
 169       interface PeripheralSide;
 170       // declare the interface to the peripherals
 171       // Each peripheral's function will be either an input, output
 172       // or be bi-directional.  an input field will be an output from the
 173       // peripheral and an output field will be an input to the peripheral.
 174       // Bi-directional functions also have an output-enable (which
 175       // again comes *in* from the peripheral)''')
 176         # ==============================================================
 177
 178         # == create method definitions for all peripheral interfaces ==#
 179         ifaces.ifacefmt2(bsv_file)
 180         bsv_file.write("\n      endinterface\n")
 181
 182         # ===== finish interface definition and start module definition=======
 183         bsv_file.write('''
 184
 185    interface Ifc_pinmux;
 186       // this interface controls how each IO cell is routed.  setting
 187       // any given IO cell's mux control value will result in redirection
 188       // of not just the input or output to different peripheral functions
 189       // but also the *direction* control - if appropriate - as well.
 190       interface MuxSelectionLines mux_lines;
 191
 192       // this interface contains the inputs, outputs and direction-control
 193       // lines for all peripherals.  GPIO is considered to also be just
 194       // a peripheral because it also has in, out and direction-control.
 195       interface PeripheralSide peripheral_side;
 196
 197       // this interface is to be linked to the individual IO cells.
 198       // if looking at a "non-muxed" GPIO design, basically the
 199       // IO cell input, output and direction-control wires are cut
 200       // (giving six pairs of dangling wires, named left and right)
 201       // these iocells are routed in their place on one side ("left")
 202       // and the matching *GPIO* peripheral interfaces in/out/dir
 203       // connect to the OTHER side ("right").  the result is that
 204       // the muxer settings end up controlling the routing of where
 205       // the I/O from the IOcell actually goes.
 206       interface IOCellSide iocell_side;
 207    endinterface
 208
 209    (*synthesize*)
 210    module mkpinmux(Ifc_pinmux);
 211 ''')
 212         # ====================================================================
 213
 214         # ======================= create wire and registers =================#
 215         bsv_file.write('''
 216       // the followins wires capture the pin-mux selection
 217       // values for each mux assigned to a CELL
 218 ''')
 219         for cell in p.muxed_cells:
 220             bsv_file.write(mux_interface.wirefmt(
 221                 cell[0], cell_bit_width))
 222
 223         iocells.wirefmt(bsv_file)
 224         ifaces.wirefmt(bsv_file)
 225
 226         bsv_file.write("\n")
 227         # ====================================================================
 228         # ========================= Actual pinmuxing ========================#
 229         bsv_file.write('''
 230       /*====== This where the muxing starts for each io-cell======*/
 231       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 232 ''')
 233         bsv_file.write(p.pinmux)
 234         bsv_file.write('''
 235       /*============================================================*/
 236 ''')
 237         # ====================================================================
 238         # ================= interface definitions for each method =============#
 239         bsv_file.write('''
 240     interface mux_lines = interface MuxSelectionLines
 241 ''')
 242         for cell in p.muxed_cells:
 243             bsv_file.write(
 244                 mux_interface.ifacedef(
 245                     cell[0], cell_bit_width))
 246         bsv_file.write("\n    endinterface;")
 247
 248         bsv_file.write('''
 249
 250     interface iocell_side = interface IOCellSide
 251 ''')
 252         iocells.ifacedef(bsv_file)
 253         bsv_file.write("\n     endinterface;")
 254
 255         bsv_file.write('''
 256
 257      interface peripheral_side = interface PeripheralSide
 258 ''')
 259         ifaces.ifacedef2(bsv_file)
 260         bsv_file.write("\n      endinterface;")
 261
 262         bsv_file.write(footer)
 263         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 264         # ======================================================================
 265
 266
 267 def write_ptp(ptp, p, ifaces):
 268     with open(ptp, 'w') as bsv_file:
 269         bsv_file.write(copyright + '''
 270 package PinTop;
 271     import pinmux::*;
 272     interface Ifc_PintTop;
 273         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 274         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 275         interface PeripheralSide peripheral_side;
 276     endinterface
 277
 278     module mkPinTop(Ifc_PintTop);
 279         // instantiate the pin-mux module here
 280         Ifc_pinmux pinmux <-mkpinmux;
 281
 282         // declare the registers which will be used to mux the IOs
 283 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 284
 285         cell_bit_width = str(p.cell_bitwidth)
 286         for cell in p.muxed_cells:
 287             bsv_file.write('''
 288                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 289                 cell_bit_width, cell[0]))
 290
 291         bsv_file.write('''
 292         // rule to connect the registers to the selection lines of the
 293         // pin-mux module
 294         rule connect_selection_registers;''')
 295
 296         for cell in p.muxed_cells:
 297             bsv_file.write('''
 298           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 299
 300         bsv_file.write('''
 301         endrule
 302         // method definitions for the write user interface
 303         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 304           Bool err=False;
 305           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 306                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 307         index = 0
 308         for cell in p.muxed_cells:
 309             bsv_file.write('''
 310             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 311             index = index + 1
 312
 313         bsv_file.write('''
 314             default: err=True;
 315           endcase
 316           return err;
 317         endmethod''')
 318
 319         bsv_file.write('''
 320         // method definitions for the read user interface
 321         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 322           Bool err=False;
 323           Bit#(32) data=0;
 324           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 325                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 326         index = 0
 327         for cell in p.muxed_cells:
 328             bsv_file.write('''
 329                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 330             index = index + 1
 331
 332         bsv_file.write('''
 333             default:err=True;
 334           endcase
 335           return tuple2(err,data);
 336         endmethod
 337         interface peripheral_side=pinmux.peripheral_side;
 338     endmodule
 339 endpackage
 340 ''')
 341
 342
 343 def write_bvp(bvp, p, ifaces):
 344     # ######## Generate bus transactors ################
 345     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 346               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 347     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 348         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 349
 350     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 351     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 352     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 353               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 354     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 355         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 356     with open(bvp, 'w') as bsv_file:
 357         # assume here that all muxes have a 1:1 gpio
 358         cfg = []
 359         decl = []
 360         idec = []
 361         iks = sorted(ifaces.keys())
 362         for iname in iks:
 363             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 364                 continue
 365             bank = iname[4:]
 366             ifc = ifaces[iname]
 367             npins = len(ifc.pinspecs)
 368             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 369                                       0,  # USERSPACE
 370                                       bank, npins))
 371             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 372                                      0,  # USERSPACE
 373                                      bank, npins))
 374             decl.append(gpiodec.format(npins, bank))
 375             decl.append(muxdec .format(npins, bank))
 376             idec.append(gpioifc.format(bank))
 377             idec.append(muxifc.format(bank))
 378         print dir(ifaces)
 379         print ifaces.items()
 380         print dir(ifaces['gpioa'])
 381         print ifaces['gpioa'].pinspecs
 382         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 383         gpiocfg = '\n'.join(cfg)
 384         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 385     # ##################################################
 386
 387
 388 def write_instances(idef, p, ifaces):
 389     with open(idef, 'w') as bsv_file:
 390         txt = '''\
 391 `define ADDR {0}
 392 `define PADDR {0}
 393 `define DATA {1}
 394 `define Reg_width {1}
 395 `define USERSPACE 0
 396
 397 // TODO: work out if these are needed
 398 `define PWM_AXI4Lite
 399 `define PRFDEPTH 6
 400 `define VADDR 39
 401 `define DCACHE_BLOCK_SIZE 4
 402 `define DCACHE_WORD_SIZE 8
 403 `define PERFMONITORS                            64
 404 `define DCACHE_WAYS 4
 405 `define DCACHE_TAG_BITS 20      // tag_bits = 52
 406 `define PLIC
 407         `define PLICBase                'h0c000000
 408         `define PLICEnd         'h10000000
 409 `define INTERRUPT_PINS 64
 410
 411 `define BAUD_RATE 130
 412 `ifdef simulate
 413   `define BAUD_RATE 5 //130 //
 414 `endif
 415 '''
 416         bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH))