src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 import GetPut::*;
  43 import Vector::*;
  44
  45 '''
  46 footer = '''
  47    endmodule
  48 endpackage
  49 '''
  50
  51
  52 def pinmuxgen(pth=None, verify=True):
  53     """ populating the file with the code
  54     """
  55
  56     p = Parse(pth, verify)
  57     iocells = Interfaces()
  58     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  59     ifaces = Interfaces(pth)
  60     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  61     init(p, ifaces)
  62
  63     bp = 'bsv_src'
  64     if pth:
  65         bp = os.path.join(pth, bp)
  66     if not os.path.exists(bp):
  67         os.makedirs(bp)
  68     bl = os.path.join(bp, 'bsv_lib')
  69     if not os.path.exists(bl):
  70         os.makedirs(bl)
  71
  72     cwd = os.path.split(__file__)[0]
  73
  74     # copy over template and library files
  75     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  76                     os.path.join(bp, 'Makefile'))
  77     cwd = os.path.join(cwd, 'bsv_lib')
  78     for fname in []:
  79         shutil.copyfile(os.path.join(cwd, fname),
  80                         os.path.join(bl, fname))
  81
  82     bus = os.path.join(bp, 'busenable.bsv')
  83     pmp = os.path.join(bp, 'pinmux.bsv')
  84     ptp = os.path.join(bp, 'PinTop.bsv')
  85     bvp = os.path.join(bp, 'bus.bsv')
  86     idef = os.path.join(bp, 'instance_defines.bsv')
  87     slow = os.path.join(bp, 'slow_peripherals.bsv')
  88     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
  89     slowmf = os.path.join(bp, 'slow_memory_map.bsv')
  90     slowmt = os.path.join(cwd, 'slow_tuple2_template.bsv')
  91     soc = os.path.join(bp, 'socgen.bsv')
  92     soct = os.path.join(cwd, 'soc_template.bsv')
  93
  94     write_pmp(pmp, p, ifaces, iocells)
  95     write_ptp(ptp, p, ifaces)
  96     write_bvp(bvp, p, ifaces)
  97     write_bus(bus, p, ifaces)
  98     write_instances(idef, p, ifaces)
  99     write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells)
 100     write_soc(soc, soct, p, ifaces, iocells)
 101
 102
 103 def write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells):
 104     """ write out the slow_peripherals.bsv file.
 105         joins all the peripherals together into one AXI Lite interface
 106     """
 107     with open(slowmt) as bsv_file:
 108         slowmt = bsv_file.read()
 109     with open(slowt) as bsv_file:
 110         slowt = bsv_file.read()
 111     imports = ifaces.slowimport()
 112     ifdecl = ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 113     regdef = ifaces.axi_reg_def()
 114     slavedecl = ifaces.axi_slave_idx()
 115     fnaddrmap = ifaces.axi_addr_map()
 116     mkslow = ifaces.mkslow_peripheral()
 117     mkcon = ifaces.mk_connection()
 118     mkcellcon = ifaces.mk_cellconn()
 119     pincon = ifaces.mk_pincon()
 120     inst = ifaces.extifinstance()
 121     inst2 = ifaces.extifinstance2()
 122     mkplic = ifaces.mk_plic()
 123     numsloirqs = ifaces.mk_sloirqsdef()
 124     ifacedef = ifaces.mk_ext_ifacedef()
 125     ifacedef = ifaces.mk_ext_ifacedef()
 126     with open(slow, "w") as bsv_file:
 127         bsv_file.write(slowt.format(imports, ifdecl, regdef, slavedecl,
 128                                     fnaddrmap, mkslow, mkcon, mkcellcon,
 129                                     pincon, inst, mkplic,
 130                                     numsloirqs, ifacedef,
 131                                     inst2))
 132     with open(slowmf, "w") as bsv_file:
 133         bsv_file.write(slowmt.format(regdef, slavedecl, fnaddrmap))
 134
 135
 136 def write_soc(soc, soct, p, ifaces, iocells):
 137     """ write out the soc.bsv file.
 138         joins all the peripherals together as AXI Masters
 139     """
 140     ifaces.fastbusmode = True  # side-effects... shouldn't really do this
 141     with open(soct) as bsv_file:
 142         soct = bsv_file.read()
 143     imports = ifaces.slowimport()
 144     ifdecl = ifaces.fastifdecl()
 145 #ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 146     regdef = ifaces.axi_fastmem_def()
 147     slavedecl = ifaces.axi_fastslave_idx()
 148     mastdecl = ifaces.axi_master_idx()
 149     fnaddrmap = ifaces.axi_addr_map()
 150     mkfast = ifaces.mkfast_peripheral()
 151     mkcon = ifaces.mk_fast_connection()
 152     mkcellcon = ifaces.mk_cellconn()
 153     pincon = ifaces.mk_pincon()
 154     inst = ifaces.extfastifinstance()
 155     mkplic = ifaces.mk_plic()
 156     numsloirqs = ifaces.mk_sloirqsdef()
 157     ifacedef = ifaces.mk_ext_ifacedef()
 158     dma = ifaces.mk_dma_irq()
 159     num_dmachannels = ifaces.num_dmachannels()
 160     with open(soc, "w") as bsv_file:
 161         bsv_file.write(soct.format(imports, ifdecl, mkfast,
 162                                    slavedecl, mastdecl, mkcon,
 163                                    inst, dma, num_dmachannels,
 164                                    pincon, regdef, fnaddrmap,
 165                                    ))
 166
 167
 168 def write_bus(bus, p, ifaces):
 169     # package and interface declaration followed by
 170     # the generic io_cell definition
 171     with open(bus, "w") as bsv_file:
 172         ifaces.busfmt(bsv_file)
 173
 174
 175 def write_pmp(pmp, p, ifaces, iocells):
 176     # package and interface declaration followed by
 177     # the generic io_cell definition
 178     with open(pmp, "w") as bsv_file:
 179         bsv_file.write(header)
 180
 181         cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
 182         bsv_file.write('''\
 183       (*always_ready,always_enabled*)
 184       interface MuxSelectionLines;
 185
 186       // declare the method which will capture the user pin-mux
 187       // selection values.The width of the input is dependent on the number
 188       // of muxes happening per IO. For now we have a generalized width
 189       // where each IO will have the same number of muxes.''')
 190
 191         for cell in p.muxed_cells:
 192             bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
 193
 194         bsv_file.write("\n      endinterface\n")
 195
 196         bsv_file.write('''
 197
 198       interface IOCellSide;
 199       // declare the interface to the IO cells.
 200       // Each IO cell will have 1 input field (output from pin mux)
 201       // and an output and out-enable field (input to pinmux)''')
 202
 203         # == create method definitions for all iocell interfaces ==#
 204         iocells.ifacefmt(bsv_file)
 205
 206         # ===== finish interface definition and start module definition=======
 207         bsv_file.write("\n      endinterface\n")
 208
 209         ifaces.ifacepfmt(bsv_file)
 210         # ===== io cell definition =======
 211         bsv_file.write('''
 212       (*always_ready,always_enabled*)
 213       interface PeripheralSide;
 214       // declare the interface to the peripherals
 215       // Each peripheral's function will be either an input, output
 216       // or be bi-directional.  an input field will be an output from the
 217       // peripheral and an output field will be an input to the peripheral.
 218       // Bi-directional functions also have an output-enable (which
 219       // again comes *in* from the peripheral)''')
 220         # ==============================================================
 221
 222         # == create method definitions for all peripheral interfaces ==#
 223         ifaces.ifacefmt2(bsv_file)
 224         bsv_file.write("\n      endinterface\n")
 225
 226         # ===== finish interface definition and start module definition=======
 227         bsv_file.write('''
 228
 229    interface Ifc_pinmux;
 230       // this interface controls how each IO cell is routed.  setting
 231       // any given IO cell's mux control value will result in redirection
 232       // of not just the input or output to different peripheral functions
 233       // but also the *direction* control - if appropriate - as well.
 234       interface MuxSelectionLines mux_lines;
 235
 236       // this interface contains the inputs, outputs and direction-control
 237       // lines for all peripherals.  GPIO is considered to also be just
 238       // a peripheral because it also has in, out and direction-control.
 239       interface PeripheralSide peripheral_side;
 240
 241       // this interface is to be linked to the individual IO cells.
 242       // if looking at a "non-muxed" GPIO design, basically the
 243       // IO cell input, output and direction-control wires are cut
 244       // (giving six pairs of dangling wires, named left and right)
 245       // these iocells are routed in their place on one side ("left")
 246       // and the matching *GPIO* peripheral interfaces in/out/dir
 247       // connect to the OTHER side ("right").  the result is that
 248       // the muxer settings end up controlling the routing of where
 249       // the I/O from the IOcell actually goes.
 250       interface IOCellSide iocell_side;
 251    endinterface
 252
 253    (*synthesize*)
 254    module mkpinmux(Ifc_pinmux);
 255 ''')
 256         # ====================================================================
 257
 258         # ======================= create wire and registers =================#
 259         bsv_file.write('''
 260       // the followins wires capture the pin-mux selection
 261       // values for each mux assigned to a CELL
 262 ''')
 263         for cell in p.muxed_cells:
 264             bsv_file.write(mux_interface.wirefmt(
 265                 cell[0], cell_bit_width))
 266
 267         iocells.wirefmt(bsv_file)
 268         ifaces.wirefmt(bsv_file)
 269
 270         bsv_file.write("\n")
 271         # ====================================================================
 272         # ========================= Actual pinmuxing ========================#
 273         bsv_file.write('''
 274       /*====== This where the muxing starts for each io-cell======*/
 275       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 276 ''')
 277         bsv_file.write(p.pinmux)
 278         bsv_file.write('''
 279       /*============================================================*/
 280 ''')
 281         # ====================================================================
 282         # ================= interface definitions for each method =============#
 283         bsv_file.write('''
 284     interface mux_lines = interface MuxSelectionLines
 285 ''')
 286         for cell in p.muxed_cells:
 287             bsv_file.write(
 288                 mux_interface.ifacedef(
 289                     cell[0], cell_bit_width))
 290         bsv_file.write("\n    endinterface;")
 291
 292         bsv_file.write('''
 293
 294     interface iocell_side = interface IOCellSide
 295 ''')
 296         iocells.ifacedef(bsv_file)
 297         bsv_file.write("\n     endinterface;")
 298
 299         bsv_file.write('''
 300
 301      interface peripheral_side = interface PeripheralSide
 302 ''')
 303         ifaces.ifacedef2(bsv_file)
 304         bsv_file.write("\n      endinterface;")
 305
 306         bsv_file.write(footer)
 307         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 308         # ======================================================================
 309
 310
 311 def write_ptp(ptp, p, ifaces):
 312     with open(ptp, 'w') as bsv_file:
 313         bsv_file.write(copyright + '''
 314 package PinTop;
 315     import pinmux::*;
 316     interface Ifc_PintTop;
 317         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 318         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 319         interface PeripheralSide peripheral_side;
 320     endinterface
 321
 322     module mkPinTop(Ifc_PintTop);
 323         // instantiate the pin-mux module here
 324         Ifc_pinmux pinmux <-mkpinmux;
 325
 326         // declare the registers which will be used to mux the IOs
 327 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 328
 329         cell_bit_width = str(p.cell_bitwidth)
 330         for cell in p.muxed_cells:
 331             bsv_file.write('''
 332                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 333                 cell_bit_width, cell[0]))
 334
 335         bsv_file.write('''
 336         // rule to connect the registers to the selection lines of the
 337         // pin-mux module
 338         rule connect_selection_registers;''')
 339
 340         for cell in p.muxed_cells:
 341             bsv_file.write('''
 342           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 343
 344         bsv_file.write('''
 345         endrule
 346         // method definitions for the write user interface
 347         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 348           Bool err=False;
 349           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 350                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 351         index = 0
 352         for cell in p.muxed_cells:
 353             bsv_file.write('''
 354             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 355             index = index + 1
 356
 357         bsv_file.write('''
 358             default: err=True;
 359           endcase
 360           return err;
 361         endmethod''')
 362
 363         bsv_file.write('''
 364         // method definitions for the read user interface
 365         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 366           Bool err=False;
 367           Bit#(32) data=0;
 368           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 369                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 370         index = 0
 371         for cell in p.muxed_cells:
 372             bsv_file.write('''
 373                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 374             index = index + 1
 375
 376         bsv_file.write('''
 377             default:err=True;
 378           endcase
 379           return tuple2(err,data);
 380         endmethod
 381         interface peripheral_side=pinmux.peripheral_side;
 382     endmodule
 383 endpackage
 384 ''')
 385
 386
 387 def write_bvp(bvp, p, ifaces):
 388     # ######## Generate bus transactors ################
 389     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 390               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 391     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 392         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 393
 394     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 395     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 396     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 397               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 398     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 399         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 400     with open(bvp, 'w') as bsv_file:
 401         # assume here that all muxes have a 1:1 gpio
 402         cfg = []
 403         decl = []
 404         idec = []
 405         iks = sorted(ifaces.keys())
 406         for iname in iks:
 407             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 408                 continue
 409             bank = iname[4:]
 410             ifc = ifaces[iname]
 411             npins = len(ifc.pinspecs)
 412             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 413                                       0,  # USERSPACE
 414                                       bank, npins))
 415             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 416                                      0,  # USERSPACE
 417                                      bank, npins))
 418             decl.append(gpiodec.format(npins, bank))
 419             decl.append(muxdec .format(npins, bank))
 420             idec.append(gpioifc.format(bank))
 421             idec.append(muxifc.format(bank))
 422         print dir(ifaces)
 423         print ifaces.items()
 424         print dir(ifaces['gpioa'])
 425         print ifaces['gpioa'].pinspecs
 426         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 427         gpiocfg = '\n'.join(cfg)
 428         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 429     # ##################################################
 430
 431
 432 def write_instances(idef, p, ifaces):
 433     with open(idef, 'w') as bsv_file:
 434         txt = '''\
 435 `define ADDR {0}
 436 `define PADDR {0}
 437 `define DATA {1}
 438 `define Reg_width {1}
 439 `define USERSPACE 0
 440 `define RV64
 441
 442 // TODO: work out if these are needed
 443 `define PWM_AXI4Lite
 444 `define PRFDEPTH 6
 445 `define VADDR 39
 446 `define DCACHE_BLOCK_SIZE 4
 447 `define DCACHE_WORD_SIZE 8
 448 `define PERFMONITORS                            64
 449 `define DCACHE_WAYS 4
 450 `define DCACHE_TAG_BITS 20      // tag_bits = 52
 451
 452 // CLINT
 453     `define ClintBase       'h02000000
 454     `define ClintEnd        'h020BFFFF
 455
 456 `define PLIC
 457         `define PLICBase                'h0c000000
 458         `define PLICEnd         'h10000000
 459 `define INTERRUPT_PINS 64
 460
 461 `define BAUD_RATE 130
 462 `ifdef simulate
 463   `define BAUD_RATE 5 //130 //
 464 `endif
 465 '''
 466         bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH))