split bsv generator into functions
[pinmux.git] / src / bsv / pinmux_generator.py
1 # ================================== Steps to add peripherals ============
2 # Step-1: create interface declaration for the peripheral to be added.
3 # Remember these are interfaces defined for the pinmux and hence
4 # will be opposite to those defined at the peripheral.
5 # For eg. the output TX from the UART will be input (method Action)
6 # for the pinmux.
7 # These changes will have to be done in interface_decl.py
8 # Step-2 define the wires that will be required to transfer data from the
9 # peripheral interface to the IO cell and vice-versa. Create a
10 # mkDWire for each input/output between the peripheral and the
11 # pinmux. Also create an implicit wire of GenericIOType for each cell
12 # that can be connected to a each bit from the peripheral.
13 # These changes will have to be done in wire_def.py
14 # Step-3: create the definitions for each of the methods defined above.
15 # These changes will have to be done in interface_decl.py
16 # ========================================================================
17
18 # default module imports
19 import os
20 import os.path
21 import time
22 import math
23
24 # project module imports
25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
26 from parse import Parse
27 from bsv.actual_pinmux import init
28 from bsv.bus_transactors import axi4_lite
29
30 copyright = '''
31 /*
32 This BSV file has been generated by the PinMux tool available at:
33 https://bitbucket.org/casl/pinmux.
34
35 Authors: Neel Gala, Luke
36 Date of generation: ''' + time.strftime("%c") + '''
37 */
38 '''
39 header = copyright + '''
40 package pinmux;
41
42 typedef struct{
43 Bit#(1) outputval; // output from core to pad bit7
44 Bit#(1) output_en; // output enable from core to pad bit6
45 Bit#(1) input_en; // input enable from core to io_cell bit5
46 Bit#(1) pullup_en; // pullup enable from core to io_cell bit4
47 Bit#(1) pulldown_en; // pulldown enable from core to io_cell bit3
48 Bit#(1) drivestrength; // drivestrength from core to io_cell bit2
49 Bit#(1) pushpull_en; // pushpull enable from core to io_cell bit1
50 Bit#(1) opendrain_en; // opendrain enable form core to io_cell bit0
51 } GenericIOType deriving(Eq,Bits,FShow);
52
53 '''
54 footer = '''
55 endinterface;
56 endmodule
57 endpackage
58 '''
59
60
61 def pinmuxgen(pth=None, verify=True):
62 """ populating the file with the code
63 """
64
65 p = Parse(pth, verify)
66 ifaces = Interfaces(pth)
67 ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
68 init(p, ifaces)
69
70 bp = 'bsv_src'
71 if pth:
72 bp = os.path.join(pth, bp)
73 if not os.path.exists(bp):
74 os.makedirs(bp)
75
76 pmp = os.path.join(bp, 'pinmux.bsv')
77 ptp = os.path.join(bp, 'PinTop.bsv')
78 bvp = os.path.join(bp, 'bus.bsv')
79
80 write_pmp(pmp, p, ifaces)
81 write_ptp(pmp, p, ifaces)
82 write_bvp(pmp, p, ifaces)
83
84
85 def write_pmp(pmp, p, ifaces):
86 # package and interface declaration followed by
87 # the generic io_cell definition
88 with open(pmp, "w") as bsv_file:
89 bsv_file.write(header)
90
91 bsv_file.write('''\
92 interface MuxSelectionLines;
93
94 // declare the method which will capture the user pin-mux
95 // selection values.The width of the input is dependent on the number
96 // of muxes happening per IO. For now we have a generalized width
97 // where each IO will have the same number of muxes.''')
98
99 for cell in p.muxed_cells:
100 cnum = 'Bit#(' + str(int(math.log(len(cell) - 1, 2))) + ')'
101 bsv_file.write(mux_interface.ifacefmt(cell[0], cnum))
102
103 bsv_file.write('''
104 endinterface
105
106 interface PeripheralSide;
107 // declare the interface to the IO cells.
108 // Each IO cell will have 8 input field (output from pin mux
109 // and on output field (input to pinmux)''')
110 # ==============================================================
111
112 # == create method definitions for all peripheral interfaces ==#
113 ifaces.ifacefmt(bsv_file)
114
115 # ==============================================================
116
117 # ===== finish interface definition and start module definition=======
118 bsv_file.write('''
119 endinterface
120
121 interface Ifc_pinmux;
122 interface MuxSelectionLines mux_lines;
123 interface PeripheralSide peripheral_side;
124 endinterface
125 (*synthesize*)
126 module mkpinmux(Ifc_pinmux);
127 ''')
128 # ====================================================================
129
130 # ======================= create wire and registers =================#
131 bsv_file.write('''
132 // the followins wires capture the pin-mux selection
133 // values for each mux assigned to a CELL
134 ''')
135 for cell in p.muxed_cells:
136 bsv_file.write(mux_interface.wirefmt(
137 cell[0], 'Bit#(' + str(int(math.log(len(cell) - 1, 2))) + ')'))
138
139 ifaces.wirefmt(bsv_file)
140
141 bsv_file.write("\n")
142 # ====================================================================
143 # ========================= Actual pinmuxing ========================#
144 bsv_file.write('''
145 /*====== This where the muxing starts for each io-cell======*/
146 ''')
147 bsv_file.write(p.pinmux)
148 bsv_file.write('''
149 /*============================================================*/
150 ''')
151 # ====================================================================
152 # ================= interface definitions for each method =============#
153 bsv_file.write('''
154 interface mux_lines = interface MuxSelectionLines
155 ''')
156 for cell in p.muxed_cells:
157 bsv_file.write(
158 mux_interface.ifacedef(
159 cell[0], 'Bit#(' + str(int(
160 math.log(
161 len(cell) - 1, 2))) + ')'))
162 bsv_file.write('''
163 endinterface;
164 interface peripheral_side = interface PeripheralSide
165 ''')
166 ifaces.ifacedef(bsv_file)
167 bsv_file.write(footer)
168 print("BSV file successfully generated: bsv_src/pinmux.bsv")
169 # ======================================================================
170
171
172 def write_ptp(ptp, p, ifaces):
173 with open(ptp, 'w') as bsv_file:
174 bsv_file.write(copyright + '''
175 package PinTop;
176 import pinmux::*;
177 interface Ifc_PintTop;
178 method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
179 method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
180 interface PeripheralSide peripheral_side;
181 endinterface
182
183 module mkPinTop(Ifc_PintTop);
184 // instantiate the pin-mux module here
185 Ifc_pinmux pinmux <-mkpinmux;
186
187 // declare the registers which will be used to mux the IOs
188 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
189
190 for cell in p.muxed_cells:
191 bsv_file.write('''
192 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
193 int(math.log(len(cell) - 1, 2)), cell[0]))
194
195 bsv_file.write('''
196 // rule to connect the registers to the selection lines of the
197 // pin-mux module
198 rule connect_selection_registers;''')
199
200 for cell in p.muxed_cells:
201 bsv_file.write('''
202 pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
203
204 bsv_file.write('''
205 endrule
206 // method definitions for the write user interface
207 method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
208 Bool err=False;
209 case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
210 p.ADDR_WIDTH, p.DATA_WIDTH))
211 index = 0
212 for cell in p.muxed_cells:
213 bsv_file.write('''
214 {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
215 index = index + 1
216
217 bsv_file.write('''
218 default: err=True;
219 endcase
220 return err;
221 endmethod''')
222
223 bsv_file.write('''
224 // method definitions for the read user interface
225 method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
226 Bool err=False;
227 Bit#(32) data=0;
228 case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
229 p.ADDR_WIDTH, p.DATA_WIDTH))
230 index = 0
231 for cell in p.muxed_cells:
232 bsv_file.write('''
233 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
234 index = index + 1
235
236 bsv_file.write('''
237 default:err=True;
238 endcase
239 return tuple2(err,data);
240 endmethod
241 interface peripheral_side=pinmux.peripheral_side;
242 endmodule
243 endpackage
244 ''')
245
246
247 def write_bvp(bvp, p, ifaces):
248 # ######## Generate bus transactors ################
249 with open(bvp, 'w') as bsv_file:
250 bsv_file.write(axi4_lite.format(p.ADDR_WIDTH, p.DATA_WIDTH))
251 # ##################################################