1 # ================================== Steps to add peripherals ============
2 # Step-1: create interface declaration for the peripheral to be added.
3 # Remember these are interfaces defined for the pinmux and hence
4 # will be opposite to those defined at the peripheral.
5 # For eg. the output TX from the UART will be input (method Action)
7 # These changes will have to be done in interface_decl.py
8 # Step-2 define the wires that will be required to transfer data from the
9 # peripheral interface to the IO cell and vice-versa. Create a
10 # mkDWire for each input/output between the peripheral and the
11 # pinmux. Also create an implicit wire of GenericIOType for each cell
12 # that can be connected to a each bit from the peripheral.
13 # These changes will have to be done in wire_def.py
14 # Step-3: create the definitions for each of the methods defined above.
15 # These changes will have to be done in interface_decl.py
16 # ========================================================================
18 # default module imports
24 # project module imports
25 from bsv
.interface_decl
import Interfaces
, mux_interface
, io_interface
26 from parse
import Parse
27 from bsv
.actual_pinmux
import init
28 from bsv
.bus_transactors
import axi4_lite
32 This BSV file has been generated by the PinMux tool available at:
33 https://bitbucket.org/casl/pinmux.
35 Authors: Neel Gala, Luke
36 Date of generation: ''' + time
.strftime("%c") + '''
39 header
= copyright
+ '''
49 def pinmuxgen(pth
=None, verify
=True):
50 """ populating the file with the code
53 p
= Parse(pth
, verify
)
54 iocells
= Interfaces()
55 iocells
.ifaceadd('io', p
.N_IO
, io_interface
, 0)
56 ifaces
= Interfaces(pth
)
57 #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
62 bp
= os
.path
.join(pth
, bp
)
63 if not os
.path
.exists(bp
):
65 bl
= os
.path
.join(bp
, 'bsv_lib')
66 if not os
.path
.exists(bl
):
69 cwd
= os
.path
.split(__file__
)[0]
71 # copy over template and library files
72 shutil
.copyfile(os
.path
.join(cwd
, 'Makefile.template'),
73 os
.path
.join(bp
, 'Makefile'))
74 cwd
= os
.path
.join(cwd
, 'bsv_lib')
75 for fname
in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv',
76 'gpio.bsv', 'mux.bsv',
77 'AXI4_Types.bsv', 'defined_types.bsv',
78 'AXI4_Fabric.bsv', 'Uart16550.bsv',
79 'AXI4_Lite_Fabric.bsv', 'ConcatReg.bsv',
80 'Uart_bs.bsv', 'RS232_modified.bsv',
81 'AXI4Lite_AXI4_Bridge.bsv',
82 'I2C_top.bsv', 'I2C_Defs.bsv',
83 'plic.bsv', 'Cur_Cycle.bsv',
84 'ClockDiv.bsv', 'axi_addr_generator.bsv',
85 'jtagdtm_new.bsv', 'jtagdefines.bsv',
87 'pwm.bsv', 'qspi.bsv', 'qspi.defs',
89 shutil
.copyfile(os
.path
.join(cwd
, fname
),
90 os
.path
.join(bl
, fname
))
92 bus
= os
.path
.join(bp
, 'busenable.bsv')
93 pmp
= os
.path
.join(bp
, 'pinmux.bsv')
94 ptp
= os
.path
.join(bp
, 'PinTop.bsv')
95 bvp
= os
.path
.join(bp
, 'bus.bsv')
96 idef
= os
.path
.join(bp
, 'instance_defines.bsv')
97 slow
= os
.path
.join(bp
, 'slow_peripherals.bsv')
98 slowt
= os
.path
.join(cwd
, 'slow_peripherals_template.bsv')
100 write_pmp(pmp
, p
, ifaces
, iocells
)
101 write_ptp(ptp
, p
, ifaces
)
102 write_bvp(bvp
, p
, ifaces
)
103 write_bus(bus
, p
, ifaces
)
104 write_instances(idef
, p
, ifaces
)
105 write_slow(slow
, slowt
, p
, ifaces
, iocells
)
108 def write_slow(slow
, template
, p
, ifaces
, iocells
):
109 """ write out the slow_peripherals.bsv file.
110 joins all the peripherals together into one AXI Lite interface
112 with
open(template
) as bsv_file
:
113 template
= bsv_file
.read()
114 imports
= ifaces
.slowimport()
115 ifdecl
= ifaces
.slowifdeclmux()
116 regdef
= ifaces
.axi_reg_def()
117 slavedecl
= ifaces
.axi_slave_idx()
118 fnaddrmap
= ifaces
.axi_addr_map()
119 mkslow
= ifaces
.mkslow_peripheral()
120 mkcon
= ifaces
.mk_connection()
121 mkcellcon
= ifaces
.mk_cellconn()
122 pincon
= ifaces
.mk_pincon()
123 inst
= ifaces
.slowifinstance()
124 mkplic
= ifaces
.mk_plic()
125 numsloirqs
= ifaces
.mk_sloirqsdef()
126 ifacedef
= ifaces
.mk_ext_ifacedef()
127 with
open(slow
, "w") as bsv_file
:
128 bsv_file
.write(template
.format(imports
, ifdecl
, regdef
, slavedecl
,
129 fnaddrmap
, mkslow
, mkcon
, mkcellcon
,
130 pincon
, inst
, mkplic
,
131 numsloirqs
, ifacedef
))
134 def write_bus(bus
, p
, ifaces
):
135 # package and interface declaration followed by
136 # the generic io_cell definition
137 with
open(bus
, "w") as bsv_file
:
138 ifaces
.busfmt(bsv_file
)
141 def write_pmp(pmp
, p
, ifaces
, iocells
):
142 # package and interface declaration followed by
143 # the generic io_cell definition
144 with
open(pmp
, "w") as bsv_file
:
145 bsv_file
.write(header
)
147 cell_bit_width
= 'Bit#(%d)' % p
.cell_bitwidth
149 interface MuxSelectionLines;
151 // declare the method which will capture the user pin-mux
152 // selection values.The width of the input is dependent on the number
153 // of muxes happening per IO. For now we have a generalized width
154 // where each IO will have the same number of muxes.''')
156 for cell
in p
.muxed_cells
:
157 bsv_file
.write(mux_interface
.ifacefmt(cell
[0], cell_bit_width
))
159 bsv_file
.write("\n endinterface\n")
163 interface IOCellSide;
164 // declare the interface to the IO cells.
165 // Each IO cell will have 1 input field (output from pin mux)
166 // and an output and out-enable field (input to pinmux)''')
168 # == create method definitions for all iocell interfaces ==#
169 iocells
.ifacefmt(bsv_file
)
171 # ===== finish interface definition and start module definition=======
172 bsv_file
.write("\n endinterface\n")
174 # ===== io cell definition =======
177 interface PeripheralSide;
178 // declare the interface to the peripherals
179 // Each peripheral's function will be either an input, output
180 // or be bi-directional. an input field will be an output from the
181 // peripheral and an output field will be an input to the peripheral.
182 // Bi-directional functions also have an output-enable (which
183 // again comes *in* from the peripheral)''')
184 # ==============================================================
186 # == create method definitions for all peripheral interfaces ==#
187 ifaces
.ifacefmt(bsv_file
)
188 bsv_file
.write("\n endinterface\n")
190 # ===== finish interface definition and start module definition=======
193 interface Ifc_pinmux;
194 // this interface controls how each IO cell is routed. setting
195 // any given IO cell's mux control value will result in redirection
196 // of not just the input or output to different peripheral functions
197 // but also the *direction* control - if appropriate - as well.
198 interface MuxSelectionLines mux_lines;
200 // this interface contains the inputs, outputs and direction-control
201 // lines for all peripherals. GPIO is considered to also be just
202 // a peripheral because it also has in, out and direction-control.
203 interface PeripheralSide peripheral_side;
205 // this interface is to be linked to the individual IO cells.
206 // if looking at a "non-muxed" GPIO design, basically the
207 // IO cell input, output and direction-control wires are cut
208 // (giving six pairs of dangling wires, named left and right)
209 // these iocells are routed in their place on one side ("left")
210 // and the matching *GPIO* peripheral interfaces in/out/dir
211 // connect to the OTHER side ("right"). the result is that
212 // the muxer settings end up controlling the routing of where
213 // the I/O from the IOcell actually goes.
214 interface IOCellSide iocell_side;
217 module mkpinmux(Ifc_pinmux);
219 # ====================================================================
221 # ======================= create wire and registers =================#
223 // the followins wires capture the pin-mux selection
224 // values for each mux assigned to a CELL
226 for cell
in p
.muxed_cells
:
227 bsv_file
.write(mux_interface
.wirefmt(
228 cell
[0], cell_bit_width
))
230 iocells
.wirefmt(bsv_file
)
231 ifaces
.wirefmt(bsv_file
)
234 # ====================================================================
235 # ========================= Actual pinmuxing ========================#
237 /*====== This where the muxing starts for each io-cell======*/
238 Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
240 bsv_file
.write(p
.pinmux
)
242 /*============================================================*/
244 # ====================================================================
245 # ================= interface definitions for each method =============#
247 interface mux_lines = interface MuxSelectionLines
249 for cell
in p
.muxed_cells
:
251 mux_interface
.ifacedef(
252 cell
[0], cell_bit_width
))
253 bsv_file
.write("\n endinterface;")
256 interface iocell_side = interface IOCellSide
258 iocells
.ifacedef(bsv_file
)
259 bsv_file
.write("\n endinterface;")
262 interface peripheral_side = interface PeripheralSide
264 ifaces
.ifacedef(bsv_file
)
265 bsv_file
.write("\n endinterface;")
267 bsv_file
.write(footer
)
268 print("BSV file successfully generated: bsv_src/pinmux.bsv")
269 # ======================================================================
272 def write_ptp(ptp
, p
, ifaces
):
273 with
open(ptp
, 'w') as bsv_file
:
274 bsv_file
.write(copyright
+ '''
277 interface Ifc_PintTop;
278 method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
279 method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
280 interface PeripheralSide peripheral_side;
283 module mkPinTop(Ifc_PintTop);
284 // instantiate the pin-mux module here
285 Ifc_pinmux pinmux <-mkpinmux;
287 // declare the registers which will be used to mux the IOs
288 '''.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
290 cell_bit_width
= str(p
.cell_bitwidth
)
291 for cell
in p
.muxed_cells
:
293 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
294 cell_bit_width
, cell
[0]))
297 // rule to connect the registers to the selection lines of the
299 rule connect_selection_registers;''')
301 for cell
in p
.muxed_cells
:
303 pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell
[0]))
307 // method definitions for the write user interface
308 method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
310 case (addr[{0}:{1}])'''.format(p
.upper_offset
, p
.lower_offset
,
311 p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
313 for cell
in p
.muxed_cells
:
315 {0}: rg_muxio_{1}<=truncate(data);'''.format(index
, cell
[0]))
325 // method definitions for the read user interface
326 method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
329 case (addr[{0}:{1}])'''.format(p
.upper_offset
, p
.lower_offset
,
330 p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
332 for cell
in p
.muxed_cells
:
334 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index
, cell
[0]))
340 return tuple2(err,data);
342 interface peripheral_side=pinmux.peripheral_side;
348 def write_bvp(bvp
, p
, ifaces
):
349 # ######## Generate bus transactors ################
350 gpiocfg
= '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
351 '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
352 muxcfg
= '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
353 '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
355 gpiodec
= '\tGPIO#({0}) mygpio{1} <- mkgpio();'
356 muxdec
= '\tMUX#({0}) mymux{1} <- mkmux();'
357 gpioifc
= '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
358 '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
359 muxifc
= '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
360 '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
361 with
open(bvp
, 'w') as bsv_file
:
362 # assume here that all muxes have a 1:1 gpio
366 iks
= sorted(ifaces
.keys())
368 if not iname
.startswith('gpio'): # TODO: declare other interfaces
372 npins
= len(ifc
.pinspecs
)
373 cfg
.append(gpiocfg
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
,
376 cfg
.append(muxcfg
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
,
379 decl
.append(gpiodec
.format(npins
, bank
))
380 decl
.append(muxdec
.format(npins
, bank
))
381 idec
.append(gpioifc
.format(bank
))
382 idec
.append(muxifc
.format(bank
))
385 print dir(ifaces
['gpioa'])
386 print ifaces
['gpioa'].pinspecs
387 gpiodecl
= '\n'.join(decl
) + '\n' + '\n'.join(idec
)
388 gpiocfg
= '\n'.join(cfg
)
389 bsv_file
.write(axi4_lite
.format(gpiodecl
, gpiocfg
))
390 # ##################################################
393 def write_instances(idef
, p
, ifaces
):
394 with
open(idef
, 'w') as bsv_file
:
399 `define Reg_width {1}
402 // TODO: work out if these are needed
406 `define DCACHE_BLOCK_SIZE 4
407 `define DCACHE_WORD_SIZE 8
408 `define PERFMONITORS 64
409 `define DCACHE_WAYS 4
410 `define DCACHE_TAG_BITS 20 // tag_bits = 52
412 `define PLICBase 'h0c000000
413 `define PLICEnd 'h10000000
414 `define INTERRUPT_PINS 64
416 `define BAUD_RATE 130
418 `define BAUD_RATE 5 //130 //
421 bsv_file
.write(txt
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
))