src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 '''
  43 footer = '''
  44    endmodule
  45 endpackage
  46 '''
  47
  48
  49 def pinmuxgen(pth=None, verify=True):
  50     """ populating the file with the code
  51     """
  52
  53     p = Parse(pth, verify)
  54     iocells = Interfaces()
  55     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  56     ifaces = Interfaces(pth)
  57     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  58     init(p, ifaces)
  59
  60     bp = 'bsv_src'
  61     if pth:
  62         bp = os.path.join(pth, bp)
  63     if not os.path.exists(bp):
  64         os.makedirs(bp)
  65     bl = os.path.join(bp, 'bsv_lib')
  66     if not os.path.exists(bl):
  67         os.makedirs(bl)
  68
  69     cwd = os.path.split(__file__)[0]
  70
  71     # copy over template and library files
  72     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  73                     os.path.join(bp, 'Makefile'))
  74     cwd = os.path.join(cwd, 'bsv_lib')
  75     for fname in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv',
  76                   'gpio.bsv', 'mux.bsv',
  77                   'AXI4_Types.bsv', 'defined_types.bsv',
  78                   'AXI4_Fabric.bsv', 'Uart16550.bsv',
  79                   'AXI4_Lite_Fabric.bsv', 'ConcatReg.bsv',
  80                   'Uart_bs.bsv', 'RS232_modified.bsv',
  81                   'AXI4Lite_AXI4_Bridge.bsv',
  82                   'I2C_top.bsv', 'I2C_Defs.bsv',
  83                   'plic.bsv', 'Cur_Cycle.bsv',
  84                   'ClockDiv.bsv', 'axi_addr_generator.bsv',
  85                   'jtagdtm_new.bsv', 'jtagdefines.bsv',
  86                   'sdcard_dummy.bsv',
  87                   'pwm.bsv', 'qspi.bsv', 'qspi.defs',
  88                   ]:
  89         shutil.copyfile(os.path.join(cwd, fname),
  90                         os.path.join(bl, fname))
  91
  92     bus = os.path.join(bp, 'busenable.bsv')
  93     pmp = os.path.join(bp, 'pinmux.bsv')
  94     ptp = os.path.join(bp, 'PinTop.bsv')
  95     bvp = os.path.join(bp, 'bus.bsv')
  96     idef = os.path.join(bp, 'instance_defines.bsv')
  97     slow = os.path.join(bp, 'slow_peripherals.bsv')
  98     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
  99
 100     write_pmp(pmp, p, ifaces, iocells)
 101     write_ptp(ptp, p, ifaces)
 102     write_bvp(bvp, p, ifaces)
 103     write_bus(bus, p, ifaces)
 104     write_instances(idef, p, ifaces)
 105     write_slow(slow, slowt, p, ifaces, iocells)
 106
 107
 108 def write_slow(slow, template, p, ifaces, iocells):
 109     """ write out the slow_peripherals.bsv file.
 110         joins all the peripherals together into one AXI Lite interface
 111     """
 112     with open(template) as bsv_file:
 113         template = bsv_file.read()
 114     imports = ifaces.slowimport()
 115     ifdecl = ifaces.slowifdeclmux()
 116     regdef = ifaces.axi_reg_def()
 117     slavedecl = ifaces.axi_slave_idx()
 118     fnaddrmap = ifaces.axi_addr_map()
 119     mkslow = ifaces.mkslow_peripheral()
 120     mkcon = ifaces.mk_connection()
 121     mkcellcon = ifaces.mk_cellconn()
 122     pincon = ifaces.mk_pincon()
 123     inst = ifaces.slowifinstance()
 124     mkplic = ifaces.mk_plic()
 125     numsloirqs = ifaces.mk_sloirqsdef()
 126     with open(slow, "w") as bsv_file:
 127         bsv_file.write(template.format(imports, ifdecl, regdef, slavedecl,
 128                                        fnaddrmap, mkslow, mkcon, mkcellcon,
 129                                        pincon, inst, mkplic,
 130                                        numsloirqs))
 131
 132
 133 def write_bus(bus, p, ifaces):
 134     # package and interface declaration followed by
 135     # the generic io_cell definition
 136     with open(bus, "w") as bsv_file:
 137         ifaces.busfmt(bsv_file)
 138
 139
 140 def write_pmp(pmp, p, ifaces, iocells):
 141     # package and interface declaration followed by
 142     # the generic io_cell definition
 143     with open(pmp, "w") as bsv_file:
 144         bsv_file.write(header)
 145
 146         cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
 147         bsv_file.write('''\
 148    interface MuxSelectionLines;
 149
 150       // declare the method which will capture the user pin-mux
 151       // selection values.The width of the input is dependent on the number
 152       // of muxes happening per IO. For now we have a generalized width
 153       // where each IO will have the same number of muxes.''')
 154
 155         for cell in p.muxed_cells:
 156             bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
 157
 158         bsv_file.write("\n      endinterface\n")
 159
 160         bsv_file.write('''
 161
 162       interface IOCellSide;
 163       // declare the interface to the IO cells.
 164       // Each IO cell will have 1 input field (output from pin mux)
 165       // and an output and out-enable field (input to pinmux)''')
 166
 167         # == create method definitions for all iocell interfaces ==#
 168         iocells.ifacefmt(bsv_file)
 169
 170         # ===== finish interface definition and start module definition=======
 171         bsv_file.write("\n      endinterface\n")
 172
 173         # ===== io cell definition =======
 174         bsv_file.write('''
 175
 176       interface PeripheralSide;
 177       // declare the interface to the peripherals
 178       // Each peripheral's function will be either an input, output
 179       // or be bi-directional.  an input field will be an output from the
 180       // peripheral and an output field will be an input to the peripheral.
 181       // Bi-directional functions also have an output-enable (which
 182       // again comes *in* from the peripheral)''')
 183         # ==============================================================
 184
 185         # == create method definitions for all peripheral interfaces ==#
 186         ifaces.ifacefmt(bsv_file)
 187         bsv_file.write("\n      endinterface\n")
 188
 189         # ===== finish interface definition and start module definition=======
 190         bsv_file.write('''
 191
 192    interface Ifc_pinmux;
 193       // this interface controls how each IO cell is routed.  setting
 194       // any given IO cell's mux control value will result in redirection
 195       // of not just the input or output to different peripheral functions
 196       // but also the *direction* control - if appropriate - as well.
 197       interface MuxSelectionLines mux_lines;
 198
 199       // this interface contains the inputs, outputs and direction-control
 200       // lines for all peripherals.  GPIO is considered to also be just
 201       // a peripheral because it also has in, out and direction-control.
 202       interface PeripheralSide peripheral_side;
 203
 204       // this interface is to be linked to the individual IO cells.
 205       // if looking at a "non-muxed" GPIO design, basically the
 206       // IO cell input, output and direction-control wires are cut
 207       // (giving six pairs of dangling wires, named left and right)
 208       // these iocells are routed in their place on one side ("left")
 209       // and the matching *GPIO* peripheral interfaces in/out/dir
 210       // connect to the OTHER side ("right").  the result is that
 211       // the muxer settings end up controlling the routing of where
 212       // the I/O from the IOcell actually goes.
 213       interface IOCellSide iocell_side;
 214    endinterface
 215    (*synthesize*)
 216    module mkpinmux(Ifc_pinmux);
 217 ''')
 218         # ====================================================================
 219
 220         # ======================= create wire and registers =================#
 221         bsv_file.write('''
 222       // the followins wires capture the pin-mux selection
 223       // values for each mux assigned to a CELL
 224 ''')
 225         for cell in p.muxed_cells:
 226             bsv_file.write(mux_interface.wirefmt(
 227                 cell[0], cell_bit_width))
 228
 229         iocells.wirefmt(bsv_file)
 230         ifaces.wirefmt(bsv_file)
 231
 232         bsv_file.write("\n")
 233         # ====================================================================
 234         # ========================= Actual pinmuxing ========================#
 235         bsv_file.write('''
 236       /*====== This where the muxing starts for each io-cell======*/
 237       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 238 ''')
 239         bsv_file.write(p.pinmux)
 240         bsv_file.write('''
 241       /*============================================================*/
 242 ''')
 243         # ====================================================================
 244         # ================= interface definitions for each method =============#
 245         bsv_file.write('''
 246     interface mux_lines = interface MuxSelectionLines
 247 ''')
 248         for cell in p.muxed_cells:
 249             bsv_file.write(
 250                 mux_interface.ifacedef(
 251                     cell[0], cell_bit_width))
 252         bsv_file.write("\n    endinterface;")
 253
 254         bsv_file.write('''
 255     interface iocell_side = interface IOCellSide
 256 ''')
 257         iocells.ifacedef(bsv_file)
 258         bsv_file.write("\n     endinterface;")
 259
 260         bsv_file.write('''
 261     interface peripheral_side = interface PeripheralSide
 262 ''')
 263         ifaces.ifacedef(bsv_file)
 264         bsv_file.write("\n     endinterface;")
 265
 266         bsv_file.write(footer)
 267         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 268         # ======================================================================
 269
 270
 271 def write_ptp(ptp, p, ifaces):
 272     with open(ptp, 'w') as bsv_file:
 273         bsv_file.write(copyright + '''
 274 package PinTop;
 275     import pinmux::*;
 276     interface Ifc_PintTop;
 277         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 278         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 279         interface PeripheralSide peripheral_side;
 280     endinterface
 281
 282     module mkPinTop(Ifc_PintTop);
 283         // instantiate the pin-mux module here
 284         Ifc_pinmux pinmux <-mkpinmux;
 285
 286         // declare the registers which will be used to mux the IOs
 287 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 288
 289         cell_bit_width = str(p.cell_bitwidth)
 290         for cell in p.muxed_cells:
 291             bsv_file.write('''
 292                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 293                 cell_bit_width, cell[0]))
 294
 295         bsv_file.write('''
 296         // rule to connect the registers to the selection lines of the
 297         // pin-mux module
 298         rule connect_selection_registers;''')
 299
 300         for cell in p.muxed_cells:
 301             bsv_file.write('''
 302           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 303
 304         bsv_file.write('''
 305         endrule
 306         // method definitions for the write user interface
 307         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 308           Bool err=False;
 309           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 310                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 311         index = 0
 312         for cell in p.muxed_cells:
 313             bsv_file.write('''
 314             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 315             index = index + 1
 316
 317         bsv_file.write('''
 318             default: err=True;
 319           endcase
 320           return err;
 321         endmethod''')
 322
 323         bsv_file.write('''
 324         // method definitions for the read user interface
 325         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 326           Bool err=False;
 327           Bit#(32) data=0;
 328           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 329                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 330         index = 0
 331         for cell in p.muxed_cells:
 332             bsv_file.write('''
 333                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 334             index = index + 1
 335
 336         bsv_file.write('''
 337             default:err=True;
 338           endcase
 339           return tuple2(err,data);
 340         endmethod
 341         interface peripheral_side=pinmux.peripheral_side;
 342     endmodule
 343 endpackage
 344 ''')
 345
 346
 347 def write_bvp(bvp, p, ifaces):
 348     # ######## Generate bus transactors ################
 349     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 350               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 351     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 352         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 353
 354     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 355     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 356     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 357               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 358     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 359         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 360     with open(bvp, 'w') as bsv_file:
 361         # assume here that all muxes have a 1:1 gpio
 362         cfg = []
 363         decl = []
 364         idec = []
 365         iks = sorted(ifaces.keys())
 366         for iname in iks:
 367             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 368                 continue
 369             bank = iname[4:]
 370             ifc = ifaces[iname]
 371             npins = len(ifc.pinspecs)
 372             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 373                                       0,  # USERSPACE
 374                                       bank, npins))
 375             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 376                                      0,  # USERSPACE
 377                                      bank, npins))
 378             decl.append(gpiodec.format(npins, bank))
 379             decl.append(muxdec .format(npins, bank))
 380             idec.append(gpioifc.format(bank))
 381             idec.append(muxifc.format(bank))
 382         print dir(ifaces)
 383         print ifaces.items()
 384         print dir(ifaces['gpioa'])
 385         print ifaces['gpioa'].pinspecs
 386         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 387         gpiocfg = '\n'.join(cfg)
 388         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 389     # ##################################################
 390
 391
 392 def write_instances(idef, p, ifaces):
 393     with open(idef, 'w') as bsv_file:
 394         txt = '''\
 395 `define ADDR {0}
 396 `define PADDR {0}
 397 `define DATA {1}
 398 `define Reg_width {1}
 399 `define USERSPACE 0
 400
 401 // TODO: work out if these are needed
 402 `define PWM_AXI4Lite
 403 `define PRFDEPTH 6
 404 `define VADDR 39
 405 `define DCACHE_BLOCK_SIZE 4
 406 `define DCACHE_WORD_SIZE 8
 407 `define PERFMONITORS                            64
 408 `define DCACHE_WAYS 4
 409 `define DCACHE_TAG_BITS 20      // tag_bits = 52
 410 `define PLIC
 411         `define PLICBase                'h0c000000
 412         `define PLICEnd         'h10000000
 413 `define INTERRUPT_PINS 64
 414
 415 `define BAUD_RATE 130
 416 `ifdef simulate
 417   `define BAUD_RATE 5 //130 //
 418 `endif
 419 '''
 420         bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH))