remove debug print
[pinmux.git] / src / bsv / pinmux_generator.py
1 # ================================== Steps to add peripherals ============
2 # Step-1: create interface declaration for the peripheral to be added.
3 # Remember these are interfaces defined for the pinmux and hence
4 # will be opposite to those defined at the peripheral.
5 # For eg. the output TX from the UART will be input (method Action)
6 # for the pinmux.
7 # These changes will have to be done in interface_decl.py
8 # Step-2 define the wires that will be required to transfer data from the
9 # peripheral interface to the IO cell and vice-versa. Create a
10 # mkDWire for each input/output between the peripheral and the
11 # pinmux. Also create an implicit wire of GenericIOType for each cell
12 # that can be connected to a each bit from the peripheral.
13 # These changes will have to be done in wire_def.py
14 # Step-3: create the definitions for each of the methods defined above.
15 # These changes will have to be done in interface_decl.py
16 # ========================================================================
17
18 # default module imports
19 import shutil
20 import os
21 import os.path
22 import time
23 import math
24
25 # project module imports
26 from bsv.interface_decl import Interfaces, mux_interface, io_interface
27 from parse import Parse
28 from bsv.actual_pinmux import init
29 from bsv.bus_transactors import axi4_lite
30
31 copyright = '''
32 /*
33 This BSV file has been generated by the PinMux tool available at:
34 https://bitbucket.org/casl/pinmux.
35
36 Authors: Neel Gala, Luke
37 Date of generation: ''' + time.strftime("%c") + '''
38 */
39 '''
40 header = copyright + '''
41 package pinmux;
42
43 // FunctionType: contains the active wires of a function. That INCLUDES
44 // GPIO (as GPIO is also a "Function"). These are what get muxed.
45 // However, only GPIO "Functions" will end up with Register SRAMs.
46 typedef struct{
47 Bit#(1) outputval; // output from function to pad bit2
48 Bit#(1) inputval; // input from pad to function bit1
49 Bit#(1) output_en; // output enable from core to pad bit0
50 } FunctionType deriving(Eq,Bits,FShow);
51
52 typedef struct{
53 Bit#(1) outputval; // output from core to pad bit7
54 Bit#(1) output_en; // output enable from core to pad bit6
55 Bit#(1) input_en; // input enable from core to io_cell bit5
56 } GenericIOType deriving(Eq,Bits,FShow);
57
58 '''
59 footer = '''
60 endinterface;
61 endmodule
62 endpackage
63 '''
64
65
66 def pinmuxgen(pth=None, verify=True):
67 """ populating the file with the code
68 """
69
70 p = Parse(pth, verify)
71 ifaces = Interfaces(pth)
72 ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
73 init(p, ifaces)
74
75 bp = 'bsv_src'
76 if pth:
77 bp = os.path.join(pth, bp)
78 if not os.path.exists(bp):
79 os.makedirs(bp)
80 bl = os.path.join(bp, 'bsv_lib')
81 if not os.path.exists(bl):
82 os.makedirs(bl)
83
84 cwd = os.path.split(__file__)[0]
85
86 # copy over template and library files
87 shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
88 os.path.join(bp, 'Makefile'))
89 cwd = os.path.join(cwd, 'bsv_lib')
90 for fname in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv']:
91 shutil.copyfile(os.path.join(cwd, fname),
92 os.path.join(bl, fname))
93
94 bus = os.path.join(bp, 'busenable.bsv')
95 pmp = os.path.join(bp, 'pinmux.bsv')
96 ptp = os.path.join(bp, 'PinTop.bsv')
97 bvp = os.path.join(bp, 'bus.bsv')
98
99 write_pmp(pmp, p, ifaces)
100 write_ptp(ptp, p, ifaces)
101 write_bvp(bvp, p, ifaces)
102 write_bus(bus, p, ifaces)
103
104
105 def write_bus(bus, p, ifaces):
106 # package and interface declaration followed by
107 # the generic io_cell definition
108 with open(bus, "w") as bsv_file:
109 ifaces.busfmt(bsv_file)
110
111
112 def get_cell_bit_width(p):
113 max_num_cells = 0
114 for cell in p.muxed_cells:
115 max_num_cells = max(len(cell) - 1, max_num_cells)
116 return int(math.log(max_num_cells+1, 2))
117
118
119 def write_pmp(pmp, p, ifaces):
120 # package and interface declaration followed by
121 # the generic io_cell definition
122 with open(pmp, "w") as bsv_file:
123 bsv_file.write(header)
124
125 cell_bit_width = 'Bit#(%d)' % get_cell_bit_width(p)
126 bsv_file.write('''\
127 interface MuxSelectionLines;
128
129 // declare the method which will capture the user pin-mux
130 // selection values.The width of the input is dependent on the number
131 // of muxes happening per IO. For now we have a generalized width
132 // where each IO will have the same number of muxes.''')
133
134 for cell in p.muxed_cells:
135 bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
136
137 bsv_file.write('''
138 endinterface
139
140 interface PeripheralSide;
141 // declare the interface to the IO cells.
142 // Each IO cell will have 8 input field (output from pin mux
143 // and on output field (input to pinmux)''')
144 # ==============================================================
145
146 # == create method definitions for all peripheral interfaces ==#
147 ifaces.ifacefmt(bsv_file)
148
149 # ==============================================================
150
151 # ===== finish interface definition and start module definition=======
152 bsv_file.write('''
153 endinterface
154
155 interface Ifc_pinmux;
156 interface MuxSelectionLines mux_lines;
157 interface PeripheralSide peripheral_side;
158 endinterface
159 (*synthesize*)
160 module mkpinmux(Ifc_pinmux);
161 ''')
162 # ====================================================================
163
164 # ======================= create wire and registers =================#
165 bsv_file.write('''
166 // the followins wires capture the pin-mux selection
167 // values for each mux assigned to a CELL
168 ''')
169 for cell in p.muxed_cells:
170 bsv_file.write(mux_interface.wirefmt(
171 cell[0], cell_bit_width))
172
173 ifaces.wirefmt(bsv_file)
174
175 bsv_file.write("\n")
176 # ====================================================================
177 # ========================= Actual pinmuxing ========================#
178 bsv_file.write('''
179 /*====== This where the muxing starts for each io-cell======*/
180 ''')
181 bsv_file.write(p.pinmux)
182 bsv_file.write('''
183 /*============================================================*/
184 ''')
185 # ====================================================================
186 # ================= interface definitions for each method =============#
187 bsv_file.write('''
188 interface mux_lines = interface MuxSelectionLines
189 ''')
190 for cell in p.muxed_cells:
191 bsv_file.write(
192 mux_interface.ifacedef(
193 cell[0], cell_bit_width))
194 bsv_file.write('''
195 endinterface;
196 interface peripheral_side = interface PeripheralSide
197 ''')
198 ifaces.ifacedef(bsv_file)
199 bsv_file.write(footer)
200 print("BSV file successfully generated: bsv_src/pinmux.bsv")
201 # ======================================================================
202
203
204 def write_ptp(ptp, p, ifaces):
205 with open(ptp, 'w') as bsv_file:
206 bsv_file.write(copyright + '''
207 package PinTop;
208 import pinmux::*;
209 interface Ifc_PintTop;
210 method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
211 method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
212 interface PeripheralSide peripheral_side;
213 endinterface
214
215 module mkPinTop(Ifc_PintTop);
216 // instantiate the pin-mux module here
217 Ifc_pinmux pinmux <-mkpinmux;
218
219 // declare the registers which will be used to mux the IOs
220 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
221
222 cell_bit_width = str(get_cell_bit_width(p))
223 for cell in p.muxed_cells:
224 bsv_file.write('''
225 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
226 cell_bit_width, cell[0]))
227
228 bsv_file.write('''
229 // rule to connect the registers to the selection lines of the
230 // pin-mux module
231 rule connect_selection_registers;''')
232
233 for cell in p.muxed_cells:
234 bsv_file.write('''
235 pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
236
237 bsv_file.write('''
238 endrule
239 // method definitions for the write user interface
240 method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
241 Bool err=False;
242 case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
243 p.ADDR_WIDTH, p.DATA_WIDTH))
244 index = 0
245 for cell in p.muxed_cells:
246 bsv_file.write('''
247 {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
248 index = index + 1
249
250 bsv_file.write('''
251 default: err=True;
252 endcase
253 return err;
254 endmethod''')
255
256 bsv_file.write('''
257 // method definitions for the read user interface
258 method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
259 Bool err=False;
260 Bit#(32) data=0;
261 case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
262 p.ADDR_WIDTH, p.DATA_WIDTH))
263 index = 0
264 for cell in p.muxed_cells:
265 bsv_file.write('''
266 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
267 index = index + 1
268
269 bsv_file.write('''
270 default:err=True;
271 endcase
272 return tuple2(err,data);
273 endmethod
274 interface peripheral_side=pinmux.peripheral_side;
275 endmodule
276 endpackage
277 ''')
278
279
280 def write_bvp(bvp, p, ifaces):
281 # ######## Generate bus transactors ################
282 with open(bvp, 'w') as bsv_file:
283 bsv_file.write(axi4_lite.format(p.ADDR_WIDTH, p.DATA_WIDTH))
284 # ##################################################