src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 import GetPut::*;
  43 import Vector::*;
  44
  45 '''
  46 footer = '''
  47    endmodule
  48 endpackage
  49 '''
  50
  51
  52 def pinmuxgen(pth=None, verify=True):
  53     """ populating the file with the code
  54     """
  55
  56     p = Parse(pth, verify)
  57     iocells = Interfaces()
  58     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  59     ifaces = Interfaces(pth)
  60     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  61     init(p, ifaces)
  62
  63     bp = 'bsv_src'
  64     if pth:
  65         bp = os.path.join(pth, bp)
  66     if not os.path.exists(bp):
  67         os.makedirs(bp)
  68     bl = os.path.join(bp, 'bsv_lib')
  69     if not os.path.exists(bl):
  70         os.makedirs(bl)
  71
  72     cwd = os.path.split(__file__)[0]
  73
  74     # copy over template and library files
  75     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  76                     os.path.join(bp, 'Makefile'))
  77     cwd = os.path.join(cwd, 'bsv_lib')
  78     for fname in []:
  79         shutil.copyfile(os.path.join(cwd, fname),
  80                         os.path.join(bl, fname))
  81
  82     bus = os.path.join(bp, 'busenable.bsv')
  83     pmp = os.path.join(bp, 'pinmux.bsv')
  84     ptp = os.path.join(bp, 'PinTop.bsv')
  85     bvp = os.path.join(bp, 'bus.bsv')
  86     idef = os.path.join(bp, 'instance_defines.bsv')
  87     slow = os.path.join(bp, 'slow_peripherals.bsv')
  88     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
  89     soc = os.path.join(bp, 'soc.bsv')
  90     soct = os.path.join(cwd, 'soc_template.bsv')
  91
  92     write_pmp(pmp, p, ifaces, iocells)
  93     write_ptp(ptp, p, ifaces)
  94     write_bvp(bvp, p, ifaces)
  95     write_bus(bus, p, ifaces)
  96     write_instances(idef, p, ifaces)
  97     write_slow(slow, slowt, p, ifaces, iocells)
  98     write_soc(soc, soct, p, ifaces, iocells)
  99
 100
 101 def write_slow(slow, slowt, p, ifaces, iocells):
 102     """ write out the slow_peripherals.bsv file.
 103         joins all the peripherals together into one AXI Lite interface
 104     """
 105     with open(slowt) as bsv_file:
 106         slowt = bsv_file.read()
 107     imports = ifaces.slowimport()
 108     ifdecl = ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 109     regdef = ifaces.axi_reg_def()
 110     slavedecl = ifaces.axi_slave_idx()
 111     fnaddrmap = ifaces.axi_addr_map()
 112     mkslow = ifaces.mkslow_peripheral()
 113     mkcon = ifaces.mk_connection()
 114     mkcellcon = ifaces.mk_cellconn()
 115     pincon = ifaces.mk_pincon()
 116     inst = ifaces.extifinstance()
 117     mkplic = ifaces.mk_plic()
 118     numsloirqs = ifaces.mk_sloirqsdef()
 119     ifacedef = ifaces.mk_ext_ifacedef()
 120     ifacedef = ifaces.mk_ext_ifacedef()
 121     with open(slow, "w") as bsv_file:
 122         bsv_file.write(slowt.format(imports, ifdecl, regdef, slavedecl,
 123                                     fnaddrmap, mkslow, mkcon, mkcellcon,
 124                                     pincon, inst, mkplic,
 125                                     numsloirqs, ifacedef))
 126
 127 def write_soc(soc, soct, p, ifaces, iocells):
 128     """ write out the soc.bsv file.
 129         joins all the peripherals together as AXI Masters
 130     """
 131     ifaces.fastbusmode = True # side-effects... shouldn't really do this
 132     with open(soct) as bsv_file:
 133         soct = bsv_file.read()
 134     imports = ifaces.slowimport()
 135     ifdecl = ifaces.fastifdecl()
 136 #ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 137     regdef = ifaces.axi_reg_def()
 138     slavedecl = ifaces.axi_fastslave_idx()
 139     mastdecl = ifaces.axi_master_idx()
 140     fnaddrmap = ifaces.axi_addr_map()
 141     mkfast = ifaces.mkfast_peripheral()
 142     mkcon = ifaces.mk_fast_connection()
 143     mkcellcon = ifaces.mk_cellconn()
 144     pincon = ifaces.mk_pincon()
 145     inst = ifaces.extifinstance()
 146     mkplic = ifaces.mk_plic()
 147     numsloirqs = ifaces.mk_sloirqsdef()
 148     ifacedef = ifaces.mk_ext_ifacedef()
 149     ifacedef = ifaces.mk_ext_ifacedef()
 150     with open(soc, "w") as bsv_file:
 151         bsv_file.write(soct.format(imports, ifdecl, mkfast,
 152                             slavedecl, mastdecl, mkcon,
 153                             #'', '' #regdef, slavedecl,
 154                             #'', mkslow, #fnaddrmap, mkslow, mkcon, mkcellcon,
 155                             #pincon, inst, mkplic,
 156                             #numsloirqs, ifacedef))
 157                                   ))
 158
 159
 160 def write_bus(bus, p, ifaces):
 161     # package and interface declaration followed by
 162     # the generic io_cell definition
 163     with open(bus, "w") as bsv_file:
 164         ifaces.busfmt(bsv_file)
 165
 166
 167 def write_pmp(pmp, p, ifaces, iocells):
 168     # package and interface declaration followed by
 169     # the generic io_cell definition
 170     with open(pmp, "w") as bsv_file:
 171         bsv_file.write(header)
 172
 173         cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
 174         bsv_file.write('''\
 175       (*always_ready,always_enabled*)
 176       interface MuxSelectionLines;
 177
 178       // declare the method which will capture the user pin-mux
 179       // selection values.The width of the input is dependent on the number
 180       // of muxes happening per IO. For now we have a generalized width
 181       // where each IO will have the same number of muxes.''')
 182
 183         for cell in p.muxed_cells:
 184             bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
 185
 186         bsv_file.write("\n      endinterface\n")
 187
 188         bsv_file.write('''
 189
 190       interface IOCellSide;
 191       // declare the interface to the IO cells.
 192       // Each IO cell will have 1 input field (output from pin mux)
 193       // and an output and out-enable field (input to pinmux)''')
 194
 195         # == create method definitions for all iocell interfaces ==#
 196         iocells.ifacefmt(bsv_file)
 197
 198         # ===== finish interface definition and start module definition=======
 199         bsv_file.write("\n      endinterface\n")
 200
 201         ifaces.ifacepfmt(bsv_file)
 202         # ===== io cell definition =======
 203         bsv_file.write('''
 204       (*always_ready,always_enabled*)
 205       interface PeripheralSide;
 206       // declare the interface to the peripherals
 207       // Each peripheral's function will be either an input, output
 208       // or be bi-directional.  an input field will be an output from the
 209       // peripheral and an output field will be an input to the peripheral.
 210       // Bi-directional functions also have an output-enable (which
 211       // again comes *in* from the peripheral)''')
 212         # ==============================================================
 213
 214         # == create method definitions for all peripheral interfaces ==#
 215         ifaces.ifacefmt2(bsv_file)
 216         bsv_file.write("\n      endinterface\n")
 217
 218         # ===== finish interface definition and start module definition=======
 219         bsv_file.write('''
 220
 221    interface Ifc_pinmux;
 222       // this interface controls how each IO cell is routed.  setting
 223       // any given IO cell's mux control value will result in redirection
 224       // of not just the input or output to different peripheral functions
 225       // but also the *direction* control - if appropriate - as well.
 226       interface MuxSelectionLines mux_lines;
 227
 228       // this interface contains the inputs, outputs and direction-control
 229       // lines for all peripherals.  GPIO is considered to also be just
 230       // a peripheral because it also has in, out and direction-control.
 231       interface PeripheralSide peripheral_side;
 232
 233       // this interface is to be linked to the individual IO cells.
 234       // if looking at a "non-muxed" GPIO design, basically the
 235       // IO cell input, output and direction-control wires are cut
 236       // (giving six pairs of dangling wires, named left and right)
 237       // these iocells are routed in their place on one side ("left")
 238       // and the matching *GPIO* peripheral interfaces in/out/dir
 239       // connect to the OTHER side ("right").  the result is that
 240       // the muxer settings end up controlling the routing of where
 241       // the I/O from the IOcell actually goes.
 242       interface IOCellSide iocell_side;
 243    endinterface
 244
 245    (*synthesize*)
 246    module mkpinmux(Ifc_pinmux);
 247 ''')
 248         # ====================================================================
 249
 250         # ======================= create wire and registers =================#
 251         bsv_file.write('''
 252       // the followins wires capture the pin-mux selection
 253       // values for each mux assigned to a CELL
 254 ''')
 255         for cell in p.muxed_cells:
 256             bsv_file.write(mux_interface.wirefmt(
 257                 cell[0], cell_bit_width))
 258
 259         iocells.wirefmt(bsv_file)
 260         ifaces.wirefmt(bsv_file)
 261
 262         bsv_file.write("\n")
 263         # ====================================================================
 264         # ========================= Actual pinmuxing ========================#
 265         bsv_file.write('''
 266       /*====== This where the muxing starts for each io-cell======*/
 267       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 268 ''')
 269         bsv_file.write(p.pinmux)
 270         bsv_file.write('''
 271       /*============================================================*/
 272 ''')
 273         # ====================================================================
 274         # ================= interface definitions for each method =============#
 275         bsv_file.write('''
 276     interface mux_lines = interface MuxSelectionLines
 277 ''')
 278         for cell in p.muxed_cells:
 279             bsv_file.write(
 280                 mux_interface.ifacedef(
 281                     cell[0], cell_bit_width))
 282         bsv_file.write("\n    endinterface;")
 283
 284         bsv_file.write('''
 285
 286     interface iocell_side = interface IOCellSide
 287 ''')
 288         iocells.ifacedef(bsv_file)
 289         bsv_file.write("\n     endinterface;")
 290
 291         bsv_file.write('''
 292
 293      interface peripheral_side = interface PeripheralSide
 294 ''')
 295         ifaces.ifacedef2(bsv_file)
 296         bsv_file.write("\n      endinterface;")
 297
 298         bsv_file.write(footer)
 299         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 300         # ======================================================================
 301
 302
 303 def write_ptp(ptp, p, ifaces):
 304     with open(ptp, 'w') as bsv_file:
 305         bsv_file.write(copyright + '''
 306 package PinTop;
 307     import pinmux::*;
 308     interface Ifc_PintTop;
 309         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 310         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 311         interface PeripheralSide peripheral_side;
 312     endinterface
 313
 314     module mkPinTop(Ifc_PintTop);
 315         // instantiate the pin-mux module here
 316         Ifc_pinmux pinmux <-mkpinmux;
 317
 318         // declare the registers which will be used to mux the IOs
 319 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 320
 321         cell_bit_width = str(p.cell_bitwidth)
 322         for cell in p.muxed_cells:
 323             bsv_file.write('''
 324                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 325                 cell_bit_width, cell[0]))
 326
 327         bsv_file.write('''
 328         // rule to connect the registers to the selection lines of the
 329         // pin-mux module
 330         rule connect_selection_registers;''')
 331
 332         for cell in p.muxed_cells:
 333             bsv_file.write('''
 334           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 335
 336         bsv_file.write('''
 337         endrule
 338         // method definitions for the write user interface
 339         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 340           Bool err=False;
 341           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 342                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 343         index = 0
 344         for cell in p.muxed_cells:
 345             bsv_file.write('''
 346             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 347             index = index + 1
 348
 349         bsv_file.write('''
 350             default: err=True;
 351           endcase
 352           return err;
 353         endmethod''')
 354
 355         bsv_file.write('''
 356         // method definitions for the read user interface
 357         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 358           Bool err=False;
 359           Bit#(32) data=0;
 360           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 361                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 362         index = 0
 363         for cell in p.muxed_cells:
 364             bsv_file.write('''
 365                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 366             index = index + 1
 367
 368         bsv_file.write('''
 369             default:err=True;
 370           endcase
 371           return tuple2(err,data);
 372         endmethod
 373         interface peripheral_side=pinmux.peripheral_side;
 374     endmodule
 375 endpackage
 376 ''')
 377
 378
 379 def write_bvp(bvp, p, ifaces):
 380     # ######## Generate bus transactors ################
 381     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 382               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 383     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 384         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 385
 386     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 387     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 388     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 389               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 390     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 391         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 392     with open(bvp, 'w') as bsv_file:
 393         # assume here that all muxes have a 1:1 gpio
 394         cfg = []
 395         decl = []
 396         idec = []
 397         iks = sorted(ifaces.keys())
 398         for iname in iks:
 399             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 400                 continue
 401             bank = iname[4:]
 402             ifc = ifaces[iname]
 403             npins = len(ifc.pinspecs)
 404             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 405                                       0,  # USERSPACE
 406                                       bank, npins))
 407             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 408                                      0,  # USERSPACE
 409                                      bank, npins))
 410             decl.append(gpiodec.format(npins, bank))
 411             decl.append(muxdec .format(npins, bank))
 412             idec.append(gpioifc.format(bank))
 413             idec.append(muxifc.format(bank))
 414         print dir(ifaces)
 415         print ifaces.items()
 416         print dir(ifaces['gpioa'])
 417         print ifaces['gpioa'].pinspecs
 418         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 419         gpiocfg = '\n'.join(cfg)
 420         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 421     # ##################################################
 422
 423
 424 def write_instances(idef, p, ifaces):
 425     with open(idef, 'w') as bsv_file:
 426         txt = '''\
 427 `define ADDR {0}
 428 `define PADDR {0}
 429 `define DATA {1}
 430 `define Reg_width {1}
 431 `define USERSPACE 0
 432
 433 // TODO: work out if these are needed
 434 `define PWM_AXI4Lite
 435 `define PRFDEPTH 6
 436 `define VADDR 39
 437 `define DCACHE_BLOCK_SIZE 4
 438 `define DCACHE_WORD_SIZE 8
 439 `define PERFMONITORS                            64
 440 `define DCACHE_WAYS 4
 441 `define DCACHE_TAG_BITS 20      // tag_bits = 52
 442 `define PLIC
 443         `define PLICBase                'h0c000000
 444         `define PLICEnd         'h10000000
 445 `define INTERRUPT_PINS 64
 446
 447 `define BAUD_RATE 130
 448 `ifdef simulate
 449   `define BAUD_RATE 5 //130 //
 450 `endif
 451 '''
 452         bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH))