whoops counting cell bit width, maths wrong
[pinmux.git] / src / bsv / pinmux_generator.py
1 # ================================== Steps to add peripherals ============
2 # Step-1: create interface declaration for the peripheral to be added.
3 # Remember these are interfaces defined for the pinmux and hence
4 # will be opposite to those defined at the peripheral.
5 # For eg. the output TX from the UART will be input (method Action)
6 # for the pinmux.
7 # These changes will have to be done in interface_decl.py
8 # Step-2 define the wires that will be required to transfer data from the
9 # peripheral interface to the IO cell and vice-versa. Create a
10 # mkDWire for each input/output between the peripheral and the
11 # pinmux. Also create an implicit wire of GenericIOType for each cell
12 # that can be connected to a each bit from the peripheral.
13 # These changes will have to be done in wire_def.py
14 # Step-3: create the definitions for each of the methods defined above.
15 # These changes will have to be done in interface_decl.py
16 # ========================================================================
17
18 # default module imports
19 import shutil
20 import os
21 import os.path
22 import time
23 import math
24
25 # project module imports
26 from bsv.interface_decl import Interfaces, mux_interface, io_interface
27 from parse import Parse
28 from bsv.actual_pinmux import init
29 from bsv.bus_transactors import axi4_lite
30
31 copyright = '''
32 /*
33 This BSV file has been generated by the PinMux tool available at:
34 https://bitbucket.org/casl/pinmux.
35
36 Authors: Neel Gala, Luke
37 Date of generation: ''' + time.strftime("%c") + '''
38 */
39 '''
40 header = copyright + '''
41 package pinmux;
42
43 // FunctionType: contains the active wires of a function. That INCLUDES
44 // GPIO (as GPIO is also a "Function"). These are what get muxed.
45 // However, only GPIO "Functions" will end up with Register SRAMs.
46 typedef struct{
47 Bit#(1) outputval; // output from function to pad bit2
48 Bit#(1) inputval; // input from pad to function bit1
49 Bit#(1) output_en; // output enable from core to pad bit0
50 } FunctionType deriving(Eq,Bits,FShow);
51
52 typedef struct{
53 Bit#(1) outputval; // output from core to pad bit7
54 Bit#(1) output_en; // output enable from core to pad bit6
55 Bit#(1) input_en; // input enable from core to io_cell bit5
56 } GenericIOType deriving(Eq,Bits,FShow);
57
58 '''
59 footer = '''
60 endinterface;
61 endmodule
62 endpackage
63 '''
64
65
66 def pinmuxgen(pth=None, verify=True):
67 """ populating the file with the code
68 """
69
70 p = Parse(pth, verify)
71 ifaces = Interfaces(pth)
72 ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
73 init(p, ifaces)
74
75 bp = 'bsv_src'
76 if pth:
77 bp = os.path.join(pth, bp)
78 if not os.path.exists(bp):
79 os.makedirs(bp)
80 bl = os.path.join(bp, 'bsv_lib')
81 if not os.path.exists(bl):
82 os.makedirs(bl)
83
84 cwd = os.path.split(__file__)[0]
85
86 # copy over template and library files
87 shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
88 os.path.join(bp, 'Makefile'))
89 cwd = os.path.join(cwd, 'bsv_lib')
90 for fname in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv']:
91 shutil.copyfile(os.path.join(cwd, fname),
92 os.path.join(bl, fname))
93
94 bus = os.path.join(bp, 'busenable.bsv')
95 pmp = os.path.join(bp, 'pinmux.bsv')
96 ptp = os.path.join(bp, 'PinTop.bsv')
97 bvp = os.path.join(bp, 'bus.bsv')
98
99 write_pmp(pmp, p, ifaces)
100 write_ptp(ptp, p, ifaces)
101 write_bvp(bvp, p, ifaces)
102 write_bus(bus, p, ifaces)
103
104
105 def write_bus(bus, p, ifaces):
106 # package and interface declaration followed by
107 # the generic io_cell definition
108 with open(bus, "w") as bsv_file:
109 ifaces.busfmt(bsv_file)
110
111
112 def get_cell_bit_width(p):
113 max_num_cells = 0
114 for cell in p.muxed_cells:
115 max_num_cells = max(len(cell) - 1, max_num_cells)
116 print max_num_cells, cell, int(math.ceil(math.log(max_num_cells, 2)))
117 return int(math.log(max_num_cells+1, 2))
118
119
120 def write_pmp(pmp, p, ifaces):
121 # package and interface declaration followed by
122 # the generic io_cell definition
123 with open(pmp, "w") as bsv_file:
124 bsv_file.write(header)
125
126 cell_bit_width = 'Bit#(%d)' % get_cell_bit_width(p)
127 bsv_file.write('''\
128 interface MuxSelectionLines;
129
130 // declare the method which will capture the user pin-mux
131 // selection values.The width of the input is dependent on the number
132 // of muxes happening per IO. For now we have a generalized width
133 // where each IO will have the same number of muxes.''')
134
135 for cell in p.muxed_cells:
136 bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
137
138 bsv_file.write('''
139 endinterface
140
141 interface PeripheralSide;
142 // declare the interface to the IO cells.
143 // Each IO cell will have 8 input field (output from pin mux
144 // and on output field (input to pinmux)''')
145 # ==============================================================
146
147 # == create method definitions for all peripheral interfaces ==#
148 ifaces.ifacefmt(bsv_file)
149
150 # ==============================================================
151
152 # ===== finish interface definition and start module definition=======
153 bsv_file.write('''
154 endinterface
155
156 interface Ifc_pinmux;
157 interface MuxSelectionLines mux_lines;
158 interface PeripheralSide peripheral_side;
159 endinterface
160 (*synthesize*)
161 module mkpinmux(Ifc_pinmux);
162 ''')
163 # ====================================================================
164
165 # ======================= create wire and registers =================#
166 bsv_file.write('''
167 // the followins wires capture the pin-mux selection
168 // values for each mux assigned to a CELL
169 ''')
170 for cell in p.muxed_cells:
171 bsv_file.write(mux_interface.wirefmt(
172 cell[0], cell_bit_width))
173
174 ifaces.wirefmt(bsv_file)
175
176 bsv_file.write("\n")
177 # ====================================================================
178 # ========================= Actual pinmuxing ========================#
179 bsv_file.write('''
180 /*====== This where the muxing starts for each io-cell======*/
181 ''')
182 bsv_file.write(p.pinmux)
183 bsv_file.write('''
184 /*============================================================*/
185 ''')
186 # ====================================================================
187 # ================= interface definitions for each method =============#
188 bsv_file.write('''
189 interface mux_lines = interface MuxSelectionLines
190 ''')
191 for cell in p.muxed_cells:
192 bsv_file.write(
193 mux_interface.ifacedef(
194 cell[0], cell_bit_width))
195 bsv_file.write('''
196 endinterface;
197 interface peripheral_side = interface PeripheralSide
198 ''')
199 ifaces.ifacedef(bsv_file)
200 bsv_file.write(footer)
201 print("BSV file successfully generated: bsv_src/pinmux.bsv")
202 # ======================================================================
203
204
205 def write_ptp(ptp, p, ifaces):
206 with open(ptp, 'w') as bsv_file:
207 bsv_file.write(copyright + '''
208 package PinTop;
209 import pinmux::*;
210 interface Ifc_PintTop;
211 method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
212 method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
213 interface PeripheralSide peripheral_side;
214 endinterface
215
216 module mkPinTop(Ifc_PintTop);
217 // instantiate the pin-mux module here
218 Ifc_pinmux pinmux <-mkpinmux;
219
220 // declare the registers which will be used to mux the IOs
221 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
222
223 cell_bit_width = str(get_cell_bit_width(p))
224 for cell in p.muxed_cells:
225 bsv_file.write('''
226 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
227 cell_bit_width, cell[0]))
228
229 bsv_file.write('''
230 // rule to connect the registers to the selection lines of the
231 // pin-mux module
232 rule connect_selection_registers;''')
233
234 for cell in p.muxed_cells:
235 bsv_file.write('''
236 pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
237
238 bsv_file.write('''
239 endrule
240 // method definitions for the write user interface
241 method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
242 Bool err=False;
243 case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
244 p.ADDR_WIDTH, p.DATA_WIDTH))
245 index = 0
246 for cell in p.muxed_cells:
247 bsv_file.write('''
248 {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
249 index = index + 1
250
251 bsv_file.write('''
252 default: err=True;
253 endcase
254 return err;
255 endmethod''')
256
257 bsv_file.write('''
258 // method definitions for the read user interface
259 method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
260 Bool err=False;
261 Bit#(32) data=0;
262 case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
263 p.ADDR_WIDTH, p.DATA_WIDTH))
264 index = 0
265 for cell in p.muxed_cells:
266 bsv_file.write('''
267 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
268 index = index + 1
269
270 bsv_file.write('''
271 default:err=True;
272 endcase
273 return tuple2(err,data);
274 endmethod
275 interface peripheral_side=pinmux.peripheral_side;
276 endmodule
277 endpackage
278 ''')
279
280
281 def write_bvp(bvp, p, ifaces):
282 # ######## Generate bus transactors ################
283 with open(bvp, 'w') as bsv_file:
284 bsv_file.write(axi4_lite.format(p.ADDR_WIDTH, p.DATA_WIDTH))
285 # ##################################################