src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 import GetPut::*;
  43 import Vector::*;
  44
  45 '''
  46 footer = '''
  47    endmodule
  48 endpackage
  49 '''
  50
  51
  52 def pinmuxgen(pth=None, verify=True):
  53     """ populating the file with the code
  54     """
  55
  56     p = Parse(pth, verify)
  57     iocells = Interfaces()
  58     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  59     ifaces = Interfaces(pth)
  60     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  61     init(p, ifaces)
  62
  63     bp = 'bsv_src'
  64     if pth:
  65         bp = os.path.join(pth, bp)
  66     if not os.path.exists(bp):
  67         os.makedirs(bp)
  68     bl = os.path.join(bp, 'bsv_lib')
  69     if not os.path.exists(bl):
  70         os.makedirs(bl)
  71
  72     cwd = os.path.split(__file__)[0]
  73
  74     # copy over template and library files
  75     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  76                     os.path.join(bp, 'Makefile'))
  77     cwd = os.path.join(cwd, 'bsv_lib')
  78     for fname in []:
  79         shutil.copyfile(os.path.join(cwd, fname),
  80                         os.path.join(bl, fname))
  81
  82     bus = os.path.join(bp, 'busenable.bsv')
  83     pmp = os.path.join(bp, 'pinmux.bsv')
  84     ptp = os.path.join(bp, 'PinTop.bsv')
  85     bvp = os.path.join(bp, 'bus.bsv')
  86     idef = os.path.join(bp, 'instance_defines.bsv')
  87     slow = os.path.join(bp, 'slow_peripherals.bsv')
  88     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
  89     slowmf = os.path.join(bp, 'slow_memory_map.bsv')
  90     slowmt = os.path.join(cwd, 'slow_tuple2_template.bsv')
  91     fastmf = os.path.join(bp, 'fast_memory_map.bsv')
  92     fastmt = os.path.join(cwd, 'fast_tuple2_template.bsv')
  93     soc = os.path.join(bp, 'socgen.bsv')
  94     soct = os.path.join(cwd, 'soc_template.bsv')
  95
  96     write_pmp(pmp, p, ifaces, iocells)
  97     write_ptp(ptp, p, ifaces)
  98     write_bvp(bvp, p, ifaces)
  99     write_bus(bus, p, ifaces)
 100     write_instances(idef, p, ifaces)
 101     write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells)
 102     write_soc(soc, soct, fastmf, fastmt, p, ifaces, iocells)
 103
 104
 105 def write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells):
 106     """ write out the slow_peripherals.bsv file.
 107         joins all the peripherals together into one AXI Lite interface
 108     """
 109     imports = ifaces.slowimport()
 110     ifdecl = ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 111     regdef = ifaces.axi_reg_def()
 112     slavedecl = ifaces.axi_slave_idx()
 113     fnaddrmap = ifaces.axi_addr_map()
 114     mkslow = ifaces.mkslow_peripheral()
 115     mkcon = ifaces.mk_connection()
 116     mkcellcon = ifaces.mk_cellconn()
 117     pincon = ifaces.mk_pincon()
 118     inst = ifaces.extifinstance()
 119     inst2 = ifaces.extifinstance2()
 120     mkplic = ifaces.mk_plic()
 121     numsloirqs = ifaces.mk_sloirqsdef()
 122     ifacedef = ifaces.mk_ext_ifacedef()
 123     ifacedef = ifaces.mk_ext_ifacedef()
 124     clockcon = ifaces.mk_slowclk_con()
 125
 126     with open(slow, "w") as bsv_file:
 127         with open(slowt) as f:
 128             slowt = f.read()
 129         bsv_file.write(slowt.format(imports, ifdecl, regdef, slavedecl,
 130                                     fnaddrmap, mkslow, mkcon, mkcellcon,
 131                                     pincon, inst, mkplic,
 132                                     numsloirqs, ifacedef,
 133                                     inst2, clockcon))
 134
 135     with open(slowmf, "w") as bsv_file:
 136         with open(slowmt) as f:
 137             slowmt = f.read()
 138         bsv_file.write(slowmt.format(regdef, slavedecl, fnaddrmap))
 139
 140
 141 def write_soc(soc, soct, fastmf, fastmt, p, ifaces, iocells):
 142     """ write out the soc.bsv file.
 143         joins all the peripherals together as AXI Masters
 144     """
 145     ifaces.fastbusmode = True  # side-effects... shouldn't really do this
 146
 147     imports = ifaces.slowimport()
 148     ifdecl = ifaces.fastifdecl()
 149     regdef = ifaces.axi_fastmem_def()
 150     slavedecl = ifaces.axi_fastslave_idx()
 151     mastdecl = ifaces.axi_master_idx()
 152     fnaddrmap = ifaces.axi_fastaddr_map()
 153     mkfast = ifaces.mkfast_peripheral()
 154     mkcon = ifaces.mk_fast_connection()
 155     mkcellcon = ifaces.mk_cellconn()
 156     pincon = ifaces.mk_fast_pincon()
 157     inst = ifaces.extfastifinstance()
 158     mkplic = ifaces.mk_plic()
 159     numsloirqs = ifaces.mk_sloirqsdef()
 160     ifacedef = ifaces.mk_ext_ifacedef()
 161     dma = ifaces.mk_dma_irq()
 162     num_dmachannels = ifaces.num_dmachannels()
 163     clockcon = ifaces.mk_fastclk_con()
 164
 165     with open(soc, "w") as bsv_file:
 166         with open(soct) as f:
 167             soct = f.read()
 168         bsv_file.write(soct.format(imports, ifdecl, mkfast,
 169                                    slavedecl, mastdecl, mkcon,
 170                                    inst, dma, num_dmachannels,
 171                                    pincon, regdef, fnaddrmap,
 172                                    clockcon,
 173                                    ))
 174
 175     with open(fastmf, "w") as bsv_file:
 176         with open(fastmt) as f:
 177             fastmt = f.read()
 178         bsv_file.write(fastmt.format(regdef, slavedecl, mastdecl, fnaddrmap))
 179
 180
 181 def write_bus(bus, p, ifaces):
 182     # package and interface declaration followed by
 183     # the generic io_cell definition
 184     with open(bus, "w") as bsv_file:
 185         ifaces.busfmt(bsv_file)
 186
 187
 188 def write_pmp(pmp, p, ifaces, iocells):
 189     # package and interface declaration followed by
 190     # the generic io_cell definition
 191     with open(pmp, "w") as bsv_file:
 192         bsv_file.write(header)
 193
 194         cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
 195         bsv_file.write('''\
 196       (*always_ready,always_enabled*)
 197       interface MuxSelectionLines;
 198
 199       // declare the method which will capture the user pin-mux
 200       // selection values.The width of the input is dependent on the number
 201       // of muxes happening per IO. For now we have a generalized width
 202       // where each IO will have the same number of muxes.''')
 203
 204         for cell in p.muxed_cells:
 205             bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
 206
 207         bsv_file.write("\n      endinterface\n")
 208
 209         bsv_file.write('''
 210
 211       interface IOCellSide;
 212       // declare the interface to the IO cells.
 213       // Each IO cell will have 1 input field (output from pin mux)
 214       // and an output and out-enable field (input to pinmux)''')
 215
 216         # == create method definitions for all iocell interfaces ==#
 217         iocells.ifacefmt(bsv_file)
 218
 219         # ===== finish interface definition and start module definition=======
 220         bsv_file.write("\n      endinterface\n")
 221
 222         ifaces.ifacepfmt(bsv_file)
 223         # ===== io cell definition =======
 224         bsv_file.write('''
 225       (*always_ready,always_enabled*)
 226       interface PeripheralSide;
 227       // declare the interface to the peripherals
 228       // Each peripheral's function will be either an input, output
 229       // or be bi-directional.  an input field will be an output from the
 230       // peripheral and an output field will be an input to the peripheral.
 231       // Bi-directional functions also have an output-enable (which
 232       // again comes *in* from the peripheral)''')
 233         # ==============================================================
 234
 235         # == create method definitions for all peripheral interfaces ==#
 236         ifaces.ifacefmt2(bsv_file)
 237         bsv_file.write("\n      endinterface\n")
 238
 239         # ===== finish interface definition and start module definition=======
 240         bsv_file.write('''
 241
 242    interface Ifc_pinmux;
 243       // this interface controls how each IO cell is routed.  setting
 244       // any given IO cell's mux control value will result in redirection
 245       // of not just the input or output to different peripheral functions
 246       // but also the *direction* control - if appropriate - as well.
 247       interface MuxSelectionLines mux_lines;
 248
 249       // this interface contains the inputs, outputs and direction-control
 250       // lines for all peripherals.  GPIO is considered to also be just
 251       // a peripheral because it also has in, out and direction-control.
 252       interface PeripheralSide peripheral_side;
 253
 254       // this interface is to be linked to the individual IO cells.
 255       // if looking at a "non-muxed" GPIO design, basically the
 256       // IO cell input, output and direction-control wires are cut
 257       // (giving six pairs of dangling wires, named left and right)
 258       // these iocells are routed in their place on one side ("left")
 259       // and the matching *GPIO* peripheral interfaces in/out/dir
 260       // connect to the OTHER side ("right").  the result is that
 261       // the muxer settings end up controlling the routing of where
 262       // the I/O from the IOcell actually goes.
 263       interface IOCellSide iocell_side;
 264    endinterface
 265
 266    (*synthesize*)
 267    module mkpinmux(Ifc_pinmux);
 268 ''')
 269         # ====================================================================
 270
 271         # ======================= create wire and registers =================#
 272         bsv_file.write('''
 273       // the followins wires capture the pin-mux selection
 274       // values for each mux assigned to a CELL
 275 ''')
 276         for cell in p.muxed_cells:
 277             bsv_file.write(mux_interface.wirefmt(
 278                 cell[0], cell_bit_width))
 279
 280         iocells.wirefmt(bsv_file)
 281         ifaces.wirefmt(bsv_file)
 282
 283         bsv_file.write("\n")
 284         # ====================================================================
 285         # ========================= Actual pinmuxing ========================#
 286         bsv_file.write('''
 287       /*====== This where the muxing starts for each io-cell======*/
 288       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 289 ''')
 290         bsv_file.write(p.pinmux)
 291         bsv_file.write('''
 292       /*============================================================*/
 293 ''')
 294         # ====================================================================
 295         # ================= interface definitions for each method =============#
 296         bsv_file.write('''
 297     interface mux_lines = interface MuxSelectionLines
 298 ''')
 299         for cell in p.muxed_cells:
 300             bsv_file.write(
 301                 mux_interface.ifacedef(
 302                     cell[0], cell_bit_width))
 303         bsv_file.write("\n    endinterface;")
 304
 305         bsv_file.write('''
 306
 307     interface iocell_side = interface IOCellSide
 308 ''')
 309         iocells.ifacedef(bsv_file)
 310         bsv_file.write("\n     endinterface;")
 311
 312         bsv_file.write('''
 313
 314      interface peripheral_side = interface PeripheralSide
 315 ''')
 316         ifaces.ifacedef2(bsv_file)
 317         bsv_file.write("\n      endinterface;")
 318
 319         bsv_file.write(footer)
 320         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 321         # ======================================================================
 322
 323
 324 def write_ptp(ptp, p, ifaces):
 325     with open(ptp, 'w') as bsv_file:
 326         bsv_file.write(copyright + '''
 327 package PinTop;
 328     import pinmux::*;
 329     interface Ifc_PintTop;
 330         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 331         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 332         interface PeripheralSide peripheral_side;
 333     endinterface
 334
 335     module mkPinTop(Ifc_PintTop);
 336         // instantiate the pin-mux module here
 337         Ifc_pinmux pinmux <-mkpinmux;
 338
 339         // declare the registers which will be used to mux the IOs
 340 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 341
 342         cell_bit_width = str(p.cell_bitwidth)
 343         for cell in p.muxed_cells:
 344             bsv_file.write('''
 345                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 346                 cell_bit_width, cell[0]))
 347
 348         bsv_file.write('''
 349         // rule to connect the registers to the selection lines of the
 350         // pin-mux module
 351         rule connect_selection_registers;''')
 352
 353         for cell in p.muxed_cells:
 354             bsv_file.write('''
 355           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 356
 357         bsv_file.write('''
 358         endrule
 359         // method definitions for the write user interface
 360         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 361           Bool err=False;
 362           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 363                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 364         index = 0
 365         for cell in p.muxed_cells:
 366             bsv_file.write('''
 367             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 368             index = index + 1
 369
 370         bsv_file.write('''
 371             default: err=True;
 372           endcase
 373           return err;
 374         endmethod''')
 375
 376         bsv_file.write('''
 377         // method definitions for the read user interface
 378         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 379           Bool err=False;
 380           Bit#(32) data=0;
 381           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 382                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 383         index = 0
 384         for cell in p.muxed_cells:
 385             bsv_file.write('''
 386                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 387             index = index + 1
 388
 389         bsv_file.write('''
 390             default:err=True;
 391           endcase
 392           return tuple2(err,data);
 393         endmethod
 394         interface peripheral_side=pinmux.peripheral_side;
 395     endmodule
 396 endpackage
 397 ''')
 398
 399
 400 def write_bvp(bvp, p, ifaces):
 401     # ######## Generate bus transactors ################
 402     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 403               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 404     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 405         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 406
 407     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 408     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 409     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 410               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 411     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 412         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 413     with open(bvp, 'w') as bsv_file:
 414         # assume here that all muxes have a 1:1 gpio
 415         cfg = []
 416         decl = []
 417         idec = []
 418         iks = sorted(ifaces.keys())
 419         for iname in iks:
 420             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 421                 continue
 422             bank = iname[4:]
 423             ifc = ifaces[iname]
 424             npins = len(ifc.pinspecs)
 425             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 426                                       0,  # USERSPACE
 427                                       bank, npins))
 428             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 429                                      0,  # USERSPACE
 430                                      bank, npins))
 431             decl.append(gpiodec.format(npins, bank))
 432             decl.append(muxdec .format(npins, bank))
 433             idec.append(gpioifc.format(bank))
 434             idec.append(muxifc.format(bank))
 435         print dir(ifaces)
 436         print ifaces.items()
 437         print dir(ifaces['gpioa'])
 438         print ifaces['gpioa'].pinspecs
 439         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 440         gpiocfg = '\n'.join(cfg)
 441         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 442     # ##################################################
 443
 444
 445 def write_instances(idef, p, ifaces):
 446     with open(idef, 'w') as bsv_file:
 447         txt = '''\
 448 `define ADDR {0}
 449 `define PADDR {2}
 450 `define DATA {1}
 451 `define Reg_width {1}
 452 `define USERSPACE 0
 453 `define RV64
 454
 455 // TODO: work out if these are needed
 456 `define PWM_AXI4Lite
 457 `define PRFDEPTH 6
 458 `define VADDR 39
 459 `define DCACHE_BLOCK_SIZE 4
 460 `define DCACHE_WORD_SIZE 8
 461 `define PERFMONITORS                            64
 462 `define DCACHE_WAYS 4
 463 `define DCACHE_TAG_BITS 20      // tag_bits = 52
 464
 465 // CLINT
 466     `define ClintBase       'h02000000
 467     `define ClintEnd        'h020BFFFF
 468
 469 `define PLIC
 470         `define PLICBase                'h0c000000
 471         `define PLICEnd         'h10000000
 472 `define INTERRUPT_PINS 64
 473
 474 `define BAUD_RATE 130
 475 `ifdef simulate
 476   `define BAUD_RATE 5 //130 //
 477 `endif
 478 '''
 479         bsv_file.write(txt.format(p.ADDR_WIDTH,
 480                                   p.DATA_WIDTH,
 481                                   p.PADDR_WIDTH))