3 """ define functions here, with their pin names and the pin type.
5 each function returns a list (or an object with a __getitem__ function)
6 containing pin name plus type specifications.
10 * "-" for an input pin,
11 * "+" for an output pin,
12 * "*" for an in/out pin
14 each function is then added to the pinspec tuple, below, as a ("NAME",
17 different functions may be added multiple times under the same NAME,
18 so that complex (or large) functions can be split into one or more
19 groups (and placed on different pinbanks).
21 eint, pwm and gpio are slightly odd in that instead of a fixed list
22 an object is returned with a __getitem__ function that accepts a
23 slice object. in this way the actual generation of the pin name
24 is delayed until it is known precisely how many pins are to be
25 generated, and that's not known immediately (or it would be if
26 every single one of the functions below had a start and end parameter
27 added). see spec.interfaces.PinGen class slice on pingroup
31 def i2s(suffix
, bank
):
32 return ['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+']
35 def emmc(suffix
, bank
):
36 emmcpins
= ['CMD+', 'CLK+']
38 emmcpins
.append("D%d*" % i
)
42 def sdmmc(suffix
, bank
):
43 sdmmcpins
= ['CMD+', 'CLK+']
45 sdmmcpins
.append("D%d*" % i
)
49 def spi(suffix
, bank
):
50 return ['CLK*', 'NSS*', 'MOSI*', 'MISO*']
53 def quadspi(suffix
, bank
):
54 return ['CK*', 'NSS*', 'IO0*', 'IO1*', 'IO2*', 'IO3*']
57 def i2c(suffix
, bank
):
58 return ['SDA*', 'SCL*']
61 def jtag(suffix
, bank
):
62 return ['MS+', 'DI-', 'DO+', 'CK+']
65 def uart(suffix
, bank
):
69 def ulpi(suffix
, bank
):
70 ulpipins
= ['CK+', 'DIR+', 'STP+', 'NXT+']
72 ulpipins
.append('D%d*' % i
)
76 def uartfull(suffix
, bank
):
77 return ['TX+', 'RX-', 'CTS-', 'RTS+']
80 def rgbttl(suffix
, bank
):
81 ttlpins
= ['CK+', 'DE+', 'HS+', 'VS+']
83 ttlpins
.append("D%d+" % i
)
87 def rgmii(suffix
, bank
):
90 buspins
.append("ERXD%d-" % i
)
92 buspins
.append("ETXD%d+" % i
)
93 buspins
+= ['ERXCK-', 'ERXERR-', 'ERXDV-',
95 'ETXEN+', 'ETXCK+', 'ECRS-',
100 def flexbus1(suffix
, bank
):
103 buspins
.append("AD%d*" % i
)
105 buspins
.append("CS%d+" % i
)
106 buspins
+= ['ALE', 'OE', 'RW', 'TA', 'CLK+',
107 'A0', 'A1', 'TS', 'TBST',
110 buspins
.append("BWE%d" % i
)
111 for i
in range(2, 6):
112 buspins
.append("CS%d+" % i
)
116 def flexbus2(suffix
, bank
):
118 for i
in range(8, 32):
119 buspins
.append("AD%d*" % i
)
123 def sdram1(suffix
, bank
):
126 buspins
.append("SDRDQM%d*" % i
)
128 buspins
.append("SDRAD%d+" % i
)
130 buspins
.append("SDRDQ%d+" % i
)
132 buspins
.append("SDRCS%d#+" % i
)
134 buspins
.append("SDRDQ%d+" % i
)
136 buspins
.append("SDRBA%d+" % i
)
137 buspins
+= ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
142 def sdram2(suffix
, bank
):
144 for i
in range(3, 6):
145 buspins
.append("SDRCS%d#+" % i
)
146 for i
in range(8, 32):
147 buspins
.append("SDRDQ%d*" % i
)
151 def mcu8080(suffix
, bank
):
154 buspins
.append("MCUD%d*" % i
)
156 buspins
.append("MCUAD%d+" % (i
+ 8))
158 buspins
.append("MCUCS%d+" % i
)
160 buspins
.append("MCUNRB%d+" % i
)
161 buspins
+= ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
166 class RangePin(object):
167 def __init__(self
, suffix
, prefix
=None):
169 self
.prefix
= prefix
or ''
171 def __getitem__(self
, s
):
173 for idx
in range(s
.start
or 0, s
.stop
or -1, s
.step
or 1):
174 res
.append("%s%d%s" % (self
.prefix
, idx
, self
.suffix
))
178 def eint(suffix
, bank
):
182 def pwm(suffix
, bank
):
186 def gpio(suffix
, bank
):
187 return ("GPIO%s" % bank
, RangePin(prefix
=bank
, suffix
="*"))
190 # list functions by name here
192 pinspec
= (('IIS', i2s
),