a9c069a45275c832212d583e72762ac9445da99b
[riscv-isa-sim.git] / hwacha / decode_hwacha_ut.h
1 #ifndef _DECODE_HWACHA_UT_H
2 #define _DECODE_HWACHA_UT_H
3
4 #include "decode.h"
5 #include "decode_hwacha.h"
6 #include "hwacha.h"
7 #include "hwacha_xcpt.h"
8
9 #undef RS1
10 #undef RS2
11 #undef WRITE_RD
12
13 static inline reg_t read_rs1(hwacha_t* h, insn_t insn, uint32_t idx)
14 {
15 if (INSN_RS1 >= h->get_ct_state()->nxpr)
16 h->take_exception(HWACHA_CAUSE_VF_ILLEGAL_REGID, VF_PC);
17 return UT_RS1(idx);
18 }
19
20 static inline reg_t read_rs2(hwacha_t* h, insn_t insn, uint32_t idx)
21 {
22 if (INSN_RS2 >= h->get_ct_state()->nxpr)
23 h->take_exception(HWACHA_CAUSE_VF_ILLEGAL_REGID, VF_PC);
24 return UT_RS2(idx);
25 }
26
27 static inline void write_rd(hwacha_t* h, insn_t insn, uint32_t idx, reg_t value)
28 {
29 if (INSN_RD >= h->get_ct_state()->nxpr)
30 h->take_exception(HWACHA_CAUSE_VF_ILLEGAL_REGID, VF_PC);
31 UT_WRITE_RD(idx, value);
32 }
33
34 #define RS1 read_rs1(h, insn, UTIDX)
35 #define RS2 read_rs2(h, insn, UTIDX)
36 #define WRITE_RD(value) write_rd(h, insn, UTIDX, value)
37
38 #undef FRS1
39 #undef FRS2
40 #undef FRS3
41 #undef WRITE_FRD
42
43 static inline reg_t read_frs1(hwacha_t* h, insn_t insn, uint32_t idx)
44 {
45 if (INSN_RS1 >= h->get_ct_state()->nfpr)
46 h->take_exception(HWACHA_CAUSE_VF_ILLEGAL_REGID, VF_PC);
47 return UT_FRS1(idx);
48 }
49
50 static inline reg_t read_frs2(hwacha_t* h, insn_t insn, uint32_t idx)
51 {
52 if (INSN_RS2 >= h->get_ct_state()->nfpr)
53 h->take_exception(HWACHA_CAUSE_VF_ILLEGAL_REGID, VF_PC);
54 return UT_FRS2(idx);
55 }
56
57 static inline reg_t read_frs3(hwacha_t* h, insn_t insn, uint32_t idx)
58 {
59 if (INSN_RS3 >= h->get_ct_state()->nfpr)
60 h->take_exception(HWACHA_CAUSE_VF_ILLEGAL_REGID, VF_PC);
61 return UT_FRS3(idx);
62 }
63
64 static inline void write_frd(hwacha_t* h, insn_t insn, uint32_t idx, reg_t value)
65 {
66 if (INSN_RD >= h->get_ct_state()->nfpr)
67 h->take_exception(HWACHA_CAUSE_VF_ILLEGAL_REGID, VF_PC);
68 UT_WRITE_FRD(idx, value);
69 }
70
71 #define FRS1 read_frs1(h, insn, UTIDX)
72 #define FRS2 read_frs2(h, insn, UTIDX)
73 #define FRS3 read_frs3(h, insn, UTIDX)
74 #define WRITE_FRD(value) write_frd(h, insn, UTIDX, value)
75
76 // we assume the vector unit has floating-point alus
77 #undef require_fp
78 #define require_fp
79
80 #include "cvt16.h"
81
82 #define HFRS1 cvt_hs(FRS1)
83 #define HFRS2 cvt_hs(FRS2)
84 #define HFRS3 cvt_hs(FRS3)
85
86 #define WRITE_HFRD(value) write_frd(h, insn, UTIDX, cvt_sh(value, RM))
87
88 #define sext16(x) ((sreg_t)(int16_t)(x))
89
90 #endif