hwacha/hwacha_disasm.cc

   1 #include "hwacha.h"
   2
   3 static const char* xpr[] = {
   4   "zero", "ra", "s0", "s1",  "s2",  "s3",  "s4",  "s5",
   5   "s6",   "s7", "s8", "s9", "s10", "s11",  "sp",  "tp",
   6   "v0",   "v1", "a0", "a1",  "a2",  "a3",  "a4",  "a5",
   7   "a6",   "a7", "t0", "t1",  "t2",  "t3",  "t4",  "gp"
   8 };
   9
  10 static const char* fpr[] = {
  11   "fs0", "fs1",  "fs2",  "fs3",  "fs4",  "fs5",  "fs6",  "fs7",
  12   "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
  13   "fv0", "fv1", "fa0",   "fa1",  "fa2",  "fa3",  "fa4",  "fa5",
  14   "fa6", "fa7", "ft0",   "ft1",  "ft2",  "ft3",  "ft4",  "ft5"
  15 };
  16
  17 static const char* vxpr[] = {
  18   "vx0",  "vx1",  "vx2",  "vx3",  "vx4",  "vx5",  "vx6",  "vx7",
  19   "vx8",  "vx9",  "vx10", "vx11", "vx12", "vx13", "vx14", "vx15",
  20   "vx16", "vx17", "vx18", "vx19", "vx20", "vx21", "vx22", "vx23",
  21   "vx24", "vx25", "vx26", "vx27", "vx28", "vx29", "vx30", "vx31"
  22 };
  23
  24 static const char* vfpr[] = {
  25   "vf0",  "vf1",  "vf2",  "vf3",  "vf4",  "vf5",  "vf6",  "vf7",
  26   "vf8",  "vf9",  "vf10", "vf11", "vf12", "vf13", "vf14", "vf15",
  27   "vf16", "vf17", "vf18", "vf19", "vf20", "vf21", "vf22", "vf23",
  28   "vf24", "vf25", "vf26", "vf27", "vf28", "vf29", "vf30", "vf31"
  29 };
  30
  31 struct : public arg_t {
  32   std::string to_string(insn_t insn) const {
  33     return xpr[insn.rs1()];
  34   }
  35 } xrs1;
  36
  37 struct : public arg_t {
  38   std::string to_string(insn_t insn) const {
  39     return xpr[insn.rs2()];
  40   }
  41 } xrs2;
  42
  43 struct : public arg_t {
  44   std::string to_string(insn_t insn) const {
  45     return xpr[insn.rd()];
  46   }
  47 } xrd;
  48
  49 struct : public arg_t {
  50   std::string to_string(insn_t insn) const {
  51     return fpr[insn.rd()];
  52   }
  53 } frd;
  54
  55 struct : public arg_t {
  56   std::string to_string(insn_t insn) const {
  57     return fpr[insn.rs1()];
  58   }
  59 } frs1;
  60
  61 struct : public arg_t {
  62   std::string to_string(insn_t insn) const {
  63     return fpr[insn.rs2()];
  64   }
  65 } frs2;
  66
  67 struct : public arg_t {
  68   std::string to_string(insn_t insn) const {
  69     return fpr[insn.rs3()];
  70   }
  71 } frs3;
  72
  73 struct : public arg_t {
  74   std::string to_string(insn_t insn) const {
  75     return vxpr[insn.rd()];
  76   }
  77 } vxrd;
  78
  79 struct : public arg_t {
  80   std::string to_string(insn_t insn) const {
  81     return vxpr[insn.rs1()];
  82   }
  83 } vxrs1;
  84
  85 struct : public arg_t {
  86   std::string to_string(insn_t insn) const {
  87     return vfpr[insn.rd()];
  88   }
  89 } vfrd;
  90
  91 struct : public arg_t {
  92   std::string to_string(insn_t insn) const {
  93     return vfpr[insn.rs1()];
  94   }
  95 } vfrs1;
  96
  97 struct : public arg_t {
  98   std::string to_string(insn_t insn) const {
  99     return std::to_string(insn.i_imm() & 0x3f);
 100   }
 101 } nxregs;
 102
 103 struct : public arg_t {
 104   std::string to_string(insn_t insn) const {
 105     return std::to_string((insn.i_imm() >> 6) & 0x3f);
 106   }
 107 } nfregs;
 108
 109 struct : public arg_t {
 110   std::string to_string(insn_t insn) const {
 111     return std::to_string((int)insn.s_imm()) + '(' + xpr[insn.rs1()] + ')';
 112   }
 113 } vf_addr;
 114
 115 std::vector<disasm_insn_t*> hwacha_t::get_disasms()
 116 {
 117   std::vector<disasm_insn_t*> insns;
 118
 119   #define DECLARE_INSN(code, match, mask) \
 120    const uint32_t match_##code = match; \
 121    const uint32_t mask_##code = mask;
 122   #include "opcodes_hwacha.h"
 123   #undef DECLARE_INSN
 124
 125   #define DISASM_INSN(name, code, extra, ...) \
 126     insns.push_back(new disasm_insn_t(name, match_##code, mask_##code | (extra), __VA_ARGS__));
 127
 128   DISASM_INSN("vsetcfg", vsetcfg, 0, {&xrs1, &nxregs, &nfregs});
 129   DISASM_INSN("vsetvl", vsetvl, 0, {&xrd, &xrs1});
 130   DISASM_INSN("vgetcfg", vgetcfg, 0, {&xrd});
 131   DISASM_INSN("vgetvl", vgetvl, 0, {&xrd});
 132
 133   DISASM_INSN("vmvv", vmvv, 0, {&vxrd, &vxrs1});
 134   DISASM_INSN("vmsv", vmsv, 0, {&vxrd, &xrs1});
 135   DISASM_INSN("vfmvv", vfmvv, 0, {&vfrd, &vfrs1});
 136   DISASM_INSN("vfmsv.s", vfmsv_s, 0, {&vfrd, &xrs1});
 137   DISASM_INSN("vfmsv.d", vfmsv_d, 0, {&vfrd, &xrs1});
 138   DISASM_INSN("vf", vf, 0, {&vf_addr});
 139
 140   DISASM_INSN("vxcptcause", vxcptcause, 0, {&xrd});
 141   DISASM_INSN("vxcptaux", vxcptaux, 0, {&xrd});
 142   DISASM_INSN("vxcptevac", vxcptevac, 0, {&xrs1});
 143   DISASM_INSN("vxcpthold", vxcpthold, 0, {&xrs1});
 144   DISASM_INSN("vxcptkill", vxcptkill, 0, {});
 145
 146   const uint32_t mask_vseglen = 0x7UL << 29;
 147
 148   #define DISASM_VMEM_INSN(name1, name2, code, ...) \
 149     DISASM_INSN(name1, code, mask_vseglen, __VA_ARGS__) \
 150     DISASM_INSN(name2, code, 0, __VA_ARGS__) \
 151
 152   DISASM_VMEM_INSN("vld", "vlsegd", vlsegd, {&vxrd, &xrs1});
 153   DISASM_VMEM_INSN("vlw", "vlsegw", vlsegw, {&vxrd, &xrs1});
 154   DISASM_VMEM_INSN("vlwu", "vlsegwu", vlsegwu, {&vxrd, &xrs1});
 155   DISASM_VMEM_INSN("vlh", "vlsegh", vlsegh, {&vxrd, &xrs1});
 156   DISASM_VMEM_INSN("vlhu", "vlseghu", vlseghu, {&vxrd, &xrs1});
 157   DISASM_VMEM_INSN("vlb", "vlsegb", vlsegb, {&vxrd, &xrs1});
 158   DISASM_VMEM_INSN("vlbu", "vlsegbu", vlsegbu, {&vxrd, &xrs1});
 159   DISASM_VMEM_INSN("vfld", "vflsegd", vflsegd, {&vfrd, &xrs1});
 160   DISASM_VMEM_INSN("vflw", "vflsegw", vflsegw, {&vfrd, &xrs1});
 161
 162   DISASM_VMEM_INSN("vlstd", "vlsegstd", vlsegstd, {&vxrd, &xrs1, &xrs2});
 163   DISASM_VMEM_INSN("vlstw", "vlsegstw", vlsegstw, {&vxrd, &xrs1, &xrs2});
 164   DISASM_VMEM_INSN("vlstwu", "vlsegstwu", vlsegstwu, {&vxrd, &xrs1, &xrs2});
 165   DISASM_VMEM_INSN("vlsth", "vlsegsth", vlsegsth, {&vxrd, &xrs1, &xrs2});
 166   DISASM_VMEM_INSN("vlsthu", "vlsegsthu", vlsegsthu, {&vxrd, &xrs1, &xrs2});
 167   DISASM_VMEM_INSN("vlstb", "vlsegstb", vlsegstb, {&vxrd, &xrs1, &xrs2});
 168   DISASM_VMEM_INSN("vlstbu", "vlsegstbu", vlsegstbu, {&vxrd, &xrs1, &xrs2});
 169   DISASM_VMEM_INSN("vflstd", "vflsegstd", vflsegstd, {&vfrd, &xrs1, &xrs2});
 170   DISASM_VMEM_INSN("vflstw", "vflsegstw", vflsegstw, {&vfrd, &xrs1, &xrs2});
 171
 172   DISASM_VMEM_INSN("vsd", "vssegd", vssegd, {&vxrd, &xrs1});
 173   DISASM_VMEM_INSN("vsw", "vssegw", vssegw, {&vxrd, &xrs1});
 174   DISASM_VMEM_INSN("vsh", "vssegh", vssegh, {&vxrd, &xrs1});
 175   DISASM_VMEM_INSN("vsb", "vssegb", vssegb, {&vxrd, &xrs1});
 176   DISASM_VMEM_INSN("vfsd", "vfssegd", vfssegd, {&vfrd, &xrs1});
 177   DISASM_VMEM_INSN("vfsw", "vfssegw", vfssegw, {&vfrd, &xrs1});
 178
 179   DISASM_VMEM_INSN("vsstd", "vssegstd", vssegstd, {&vxrd, &xrs1, &xrs2});
 180   DISASM_VMEM_INSN("vsstw", "vssegstw", vssegstw, {&vxrd, &xrs1, &xrs2});
 181   DISASM_VMEM_INSN("vssth", "vssegsth", vssegsth, {&vxrd, &xrs1, &xrs2});
 182   DISASM_VMEM_INSN("vsstb", "vssegstb", vssegstb, {&vxrd, &xrs1, &xrs2});
 183   DISASM_VMEM_INSN("vfsstd", "vfssegstd", vfssegstd, {&vfrd, &xrs1, &xrs2});
 184   DISASM_VMEM_INSN("vfsstw", "vfssegstw", vfssegstw, {&vfrd, &xrs1, &xrs2});
 185
 186   #define DECLARE_INSN(code, match, mask) \
 187    const uint32_t match_##code = match; \
 188    const uint32_t mask_##code = mask;
 189   #include "opcodes_hwacha_ut.h"
 190   #undef DECLARE_INSN
 191
 192   #define DISASM_UT_INSN(name, code, extra, ...) \
 193     ut_disassembler.add_insn(new disasm_insn_t(name, match_##code, mask_##code | (extra), __VA_ARGS__));
 194
 195   DISASM_UT_INSN("stop", ut_stop, 0, {});
 196   DISASM_UT_INSN("utidx", ut_utidx, 0, {&xrd});
 197   DISASM_UT_INSN("movz", ut_movz, 0, {&xrd, &xrs1, &xrs2});
 198   DISASM_UT_INSN("movn", ut_movn, 0, {&xrd, &xrs1, &xrs2});
 199   DISASM_UT_INSN("fmovz", ut_fmovz, 0, {&frd, &xrs1, &frs2});
 200   DISASM_UT_INSN("fmovn", ut_fmovn, 0, {&frd, &xrs1, &frs2});
 201
 202   return insns;
 203 }