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90872edcd86148767a2addda0c8735dcf61b4cfb
[riscv-isa-sim.git]
/
hwacha
/
insns_ut
/
ut_flh.h
1
require_fp
;
2
WRITE_FRD
(
MMU
.
load_int16
(
RS1
+
insn
.
i_imm
()));
projects / riscv-isa-sim.git / blob