32d3aa68d66493f580ce17f2f6499c58f04f80ef
[riscv-isa-sim.git] / hwacha / insns_ut / ut_fmax_h.h
1 require_fp;
2 WRITE_HFRD(isNaNF32UI(HFRS2) || f32_le_quiet(HFRS2,HFRS1) /* && FRS1 not NaN */
3 ? HFRS1 : HFRS2);
4 set_fp_exceptions;