riscv/debug_defines.h

   1 #define DTM_IDCODE                          0x01
   2 /*
   3 * Identifies the release version of this part.
   4  */
   5 #define DTM_IDCODE_VERSION_OFFSET           28
   6 #define DTM_IDCODE_VERSION_LENGTH           4
   7 #define DTM_IDCODE_VERSION                  (0xfU << DTM_IDCODE_VERSION_OFFSET)
   8 /*
   9 * Identifies the designer's part number of this part.
  10  */
  11 #define DTM_IDCODE_PARTNUMBER_OFFSET        12
  12 #define DTM_IDCODE_PARTNUMBER_LENGTH        16
  13 #define DTM_IDCODE_PARTNUMBER               (0xffffU << DTM_IDCODE_PARTNUMBER_OFFSET)
  14 /*
  15 * Identifies the designer/manufacturer of this part. Bits 6:0 must be
  16 * bits 6:0 of the designer/manufacturer's Identification Code as
  17 * assigned by JEDEC Standard JEP106. Bits 10:7 contain the modulo-16
  18 * count of the number of continuation characters (0x7f) in that same
  19 * Identification Code.
  20  */
  21 #define DTM_IDCODE_MANUFID_OFFSET           1
  22 #define DTM_IDCODE_MANUFID_LENGTH           11
  23 #define DTM_IDCODE_MANUFID                  (0x7ffU << DTM_IDCODE_MANUFID_OFFSET)
  24 #define DTM_IDCODE_1_OFFSET                 0
  25 #define DTM_IDCODE_1_LENGTH                 1
  26 #define DTM_IDCODE_1                        (0x1U << DTM_IDCODE_1_OFFSET)
  27 #define DTM_DTMCS                           0x10
  28 /*
  29 * Writing 1 to this bit does a hard reset of the DTM,
  30 * causing the DTM to forget about any outstanding DMI transactions.
  31 * In general this should only be used when the Debugger has
  32 * reason to expect that the outstanding DMI transaction will never
  33 * complete (e.g. a reset condition caused an inflight DMI transaction to
  34 * be cancelled).
  35  */
  36 #define DTM_DTMCS_DMIHARDRESET_OFFSET       17
  37 #define DTM_DTMCS_DMIHARDRESET_LENGTH       1
  38 #define DTM_DTMCS_DMIHARDRESET              (0x1U << DTM_DTMCS_DMIHARDRESET_OFFSET)
  39 /*
  40 * Writing 1 to this bit clears the sticky error state
  41 * and allows the DTM to retry or complete the previous
  42 * transaction.
  43  */
  44 #define DTM_DTMCS_DMIRESET_OFFSET           16
  45 #define DTM_DTMCS_DMIRESET_LENGTH           1
  46 #define DTM_DTMCS_DMIRESET                  (0x1U << DTM_DTMCS_DMIRESET_OFFSET)
  47 /*
  48 * This is a hint to the debugger of the minimum number of
  49 * cycles a debugger should spend in
  50 * Run-Test/Idle after every DMI scan to avoid a `busy'
  51 * return code (\Fdmistat of 3). A debugger must still
  52 * check \Fdmistat when necessary.
  53 *
  54 * 0: It is not necessary to enter Run-Test/Idle at all.
  55 *
  56 * 1: Enter Run-Test/Idle and leave it immediately.
  57 *
  58 * 2: Enter Run-Test/Idle and stay there for 1 cycle before leaving.
  59 *
  60 * And so on.
  61  */
  62 #define DTM_DTMCS_IDLE_OFFSET               12
  63 #define DTM_DTMCS_IDLE_LENGTH               3
  64 #define DTM_DTMCS_IDLE                      (0x7U << DTM_DTMCS_IDLE_OFFSET)
  65 /*
  66 * 0: No error.
  67 *
  68 * 1: Reserved. Interpret the same as 2.
  69 *
  70 * 2: An operation failed (resulted in \Fop of 2).
  71 *
  72 * 3: An operation was attempted while a DMI access was still in
  73 * progress (resulted in \Fop of 3).
  74  */
  75 #define DTM_DTMCS_DMISTAT_OFFSET            10
  76 #define DTM_DTMCS_DMISTAT_LENGTH            2
  77 #define DTM_DTMCS_DMISTAT                   (0x3U << DTM_DTMCS_DMISTAT_OFFSET)
  78 /*
  79 * The size of \Faddress in \Rdmi.
  80  */
  81 #define DTM_DTMCS_ABITS_OFFSET              4
  82 #define DTM_DTMCS_ABITS_LENGTH              6
  83 #define DTM_DTMCS_ABITS                     (0x3fU << DTM_DTMCS_ABITS_OFFSET)
  84 /*
  85 * 0: Version described in spec version 0.11.
  86 *
  87 * 1: Version described in spec version 0.13 (and later?), which
  88 * reduces the DMI data width to 32 bits.
  89 *
  90 * 15: Version not described in any available version of this spec.
  91  */
  92 #define DTM_DTMCS_VERSION_OFFSET            0
  93 #define DTM_DTMCS_VERSION_LENGTH            4
  94 #define DTM_DTMCS_VERSION                   (0xfU << DTM_DTMCS_VERSION_OFFSET)
  95 #define DTM_DMI                             0x11
  96 /*
  97 * Address used for DMI access. In Update-DR this value is used
  98 * to access the DM over the DMI.
  99  */
 100 #define DTM_DMI_ADDRESS_OFFSET              34
 101 #define DTM_DMI_ADDRESS_LENGTH              abits
 102 #define DTM_DMI_ADDRESS                     (((1L<<abits)-1) << DTM_DMI_ADDRESS_OFFSET)
 103 /*
 104 * The data to send to the DM over the DMI during Update-DR, and
 105 * the data returned from the DM as a result of the previous operation.
 106  */
 107 #define DTM_DMI_DATA_OFFSET                 2
 108 #define DTM_DMI_DATA_LENGTH                 32
 109 #define DTM_DMI_DATA                        (0xffffffffULL << DTM_DMI_DATA_OFFSET)
 110 /*
 111 * When the debugger writes this field, it has the following meaning:
 112 *
 113 * 0: Ignore \Fdata and \Faddress. (nop)
 114 *
 115 * Don't send anything over the DMI during Update-DR.
 116 * This operation should never result in a busy or error response.
 117 * The address and data reported in the following Capture-DR
 118 * are undefined.
 119 *
 120 * 1: Read from \Faddress. (read)
 121 *
 122 * 2: Write \Fdata to \Faddress. (write)
 123 *
 124 * 3: Reserved.
 125 *
 126 * When the debugger reads this field, it means the following:
 127 *
 128 * 0: The previous operation completed successfully.
 129 *
 130 * 1: Reserved.
 131 *
 132 * 2: A previous operation failed.  The data scanned into \Rdmi in
 133 * this access will be ignored.  This status is sticky and can be
 134 * cleared by writing \Fdmireset in \Rdtmcs.
 135 *
 136 * This indicates that the DM itself responded with an error.
 137 * Note: there are no specified cases in which the DM would
 138 * respond with an error, and DMI is not required to support
 139 * returning errors.
 140 *
 141 * 3: An operation was attempted while a DMI request is still in
 142 * progress. The data scanned into \Rdmi in this access will be
 143 * ignored. This status is sticky and can be cleared by writing
 144 * \Fdmireset in \Rdtmcs. If a debugger sees this status, it
 145 * needs to give the target more TCK edges between Update-DR and
 146 * Capture-DR. The simplest way to do that is to add extra transitions
 147 * in Run-Test/Idle.
 148 *
 149 * (The DTM, DM, and/or component may be in different clock domains,
 150 * so synchronization may be required. Some relatively fixed number of
 151 * TCK ticks may be needed for the request to reach the DM, complete,
 152 * and for the response to be synchronized back into the TCK domain.)
 153  */
 154 #define DTM_DMI_OP_OFFSET                   0
 155 #define DTM_DMI_OP_LENGTH                   2
 156 #define DTM_DMI_OP                          (0x3ULL << DTM_DMI_OP_OFFSET)
 157 #define CSR_DCSR                            0x7b0
 158 /*
 159 * 0: There is no external debug support.
 160 *
 161 * 4: External debug support exists as it is described in this document.
 162 *
 163 * 15: There is external debug support, but it does not conform to any
 164 * available version of this spec.
 165  */
 166 #define CSR_DCSR_XDEBUGVER_OFFSET           28
 167 #define CSR_DCSR_XDEBUGVER_LENGTH           4
 168 #define CSR_DCSR_XDEBUGVER                  (0xfU << CSR_DCSR_XDEBUGVER_OFFSET)
 169 /*
 170 * When 1, {\tt ebreak} instructions in Machine Mode enter Debug Mode.
 171  */
 172 #define CSR_DCSR_EBREAKM_OFFSET             15
 173 #define CSR_DCSR_EBREAKM_LENGTH             1
 174 #define CSR_DCSR_EBREAKM                    (0x1U << CSR_DCSR_EBREAKM_OFFSET)
 175 /*
 176 * When 1, {\tt ebreak} instructions in Supervisor Mode enter Debug Mode.
 177  */
 178 #define CSR_DCSR_EBREAKS_OFFSET             13
 179 #define CSR_DCSR_EBREAKS_LENGTH             1
 180 #define CSR_DCSR_EBREAKS                    (0x1U << CSR_DCSR_EBREAKS_OFFSET)
 181 /*
 182 * When 1, {\tt ebreak} instructions in User/Application Mode enter
 183 * Debug Mode.
 184  */
 185 #define CSR_DCSR_EBREAKU_OFFSET             12
 186 #define CSR_DCSR_EBREAKU_LENGTH             1
 187 #define CSR_DCSR_EBREAKU                    (0x1U << CSR_DCSR_EBREAKU_OFFSET)
 188 /*
 189 * 0: Interrupts are disabled during single stepping.
 190 *
 191 * 1: Interrupts are enabled during single stepping.
 192 *
 193 * Implementations may hard wire this bit to 0.
 194 * The debugger must read back the value it
 195 * writes to check whether the feature is supported. If not
 196 * supported, interrupt behavior can be emulated by the debugger.
 197  */
 198 #define CSR_DCSR_STEPIE_OFFSET              11
 199 #define CSR_DCSR_STEPIE_LENGTH              1
 200 #define CSR_DCSR_STEPIE                     (0x1U << CSR_DCSR_STEPIE_OFFSET)
 201 /*
 202 * 0: Increment counters as usual.
 203 *
 204 * 1: Don't increment any counters while in Debug Mode or on {\tt
 205 * ebreak} instructions that cause entry into Debug Mode.  These
 206 * counters include the {\tt cycle} and {\tt instret} CSRs. This is
 207 * preferred for most debugging scenarios.
 208 *
 209 * An implementation may choose not to support writing to this bit.
 210 * The debugger must read back the value it writes to check whether
 211 * the feature is supported.
 212  */
 213 #define CSR_DCSR_STOPCOUNT_OFFSET           10
 214 #define CSR_DCSR_STOPCOUNT_LENGTH           1
 215 #define CSR_DCSR_STOPCOUNT                  (0x1U << CSR_DCSR_STOPCOUNT_OFFSET)
 216 /*
 217 * 0: Increment timers as usual.
 218 *
 219 * 1: Don't increment any hart-local timers while in Debug Mode.
 220 *
 221 * An implementation may choose not to support writing to this bit.
 222 * The debugger must read back the value it writes to check whether
 223 * the feature is supported.
 224  */
 225 #define CSR_DCSR_STOPTIME_OFFSET            9
 226 #define CSR_DCSR_STOPTIME_LENGTH            1
 227 #define CSR_DCSR_STOPTIME                   (0x1U << CSR_DCSR_STOPTIME_OFFSET)
 228 /*
 229 * Explains why Debug Mode was entered.
 230 *
 231 * When there are multiple reasons to enter Debug Mode in a single
 232 * cycle, the cause with the highest priority is the one written.
 233 *
 234 * 1: An {\tt ebreak} instruction was executed. (priority 3)
 235 *
 236 * 2: The Trigger Module caused a breakpoint exception. (priority 4)
 237 *
 238 * 3: The debugger requested entry to Debug Mode. (priority 2)
 239 *
 240 * 4: The hart single stepped because \Fstep was set. (priority 1)
 241 *
 242 * Other values are reserved for future use.
 243  */
 244 #define CSR_DCSR_CAUSE_OFFSET               6
 245 #define CSR_DCSR_CAUSE_LENGTH               3
 246 #define CSR_DCSR_CAUSE                      (0x7U << CSR_DCSR_CAUSE_OFFSET)
 247 /*
 248 * When set and not in Debug Mode, the hart will only execute a single
 249 * instruction and then enter Debug Mode.
 250 * If the instruction does not complete due to an exception,
 251 * the hart will immediately enter Debug Mode before executing
 252 * the trap handler, with appropriate exception registers set.
 253  */
 254 #define CSR_DCSR_STEP_OFFSET                2
 255 #define CSR_DCSR_STEP_LENGTH                1
 256 #define CSR_DCSR_STEP                       (0x1U << CSR_DCSR_STEP_OFFSET)
 257 /*
 258 * Contains the privilege level the hart was operating in when Debug
 259 * Mode was entered. The encoding is described in Table
 260 * \ref{tab:privlevel}.  A debugger can change this value to change
 261 * the hart's privilege level when exiting Debug Mode.
 262 *
 263 * Not all privilege levels are supported on all harts. If the
 264 * encoding written is not supported or the debugger is not allowed to
 265 * change to it, the hart may change to any supported privilege level.
 266  */
 267 #define CSR_DCSR_PRV_OFFSET                 0
 268 #define CSR_DCSR_PRV_LENGTH                 2
 269 #define CSR_DCSR_PRV                        (0x3U << CSR_DCSR_PRV_OFFSET)
 270 #define CSR_DPC                             0x7b1
 271 #define CSR_DPC_DPC_OFFSET                  0
 272 #define CSR_DPC_DPC_LENGTH                  XLEN
 273 #define CSR_DPC_DPC                         (((1L<<XLEN)-1) << CSR_DPC_DPC_OFFSET)
 274 #define CSR_DSCRATCH0                       0x7b2
 275 #define CSR_DSCRATCH1                       0x7b3
 276 #define CSR_TSELECT                         0x7a0
 277 #define CSR_TSELECT_INDEX_OFFSET            0
 278 #define CSR_TSELECT_INDEX_LENGTH            XLEN
 279 #define CSR_TSELECT_INDEX                   (((1L<<XLEN)-1) << CSR_TSELECT_INDEX_OFFSET)
 280 #define CSR_TDATA1                          0x7a1
 281 /*
 282 * 0: There is no trigger at this \Rtselect.
 283 *
 284 * 1: The trigger is a legacy SiFive address match trigger. These
 285 * should not be implemented and aren't further documented here.
 286 *
 287 * 2: The trigger is an address/data match trigger. The remaining bits
 288 * in this register act as described in \Rmcontrol.
 289 *
 290 * 3: The trigger is an instruction count trigger. The remaining bits
 291 * in this register act as described in \Ricount.
 292 *
 293 * 15: This trigger exists (so enumeration shouldn't terminate), but
 294 * is not currently available.
 295 *
 296 * Other values are reserved for future use.
 297  */
 298 #define CSR_TDATA1_TYPE_OFFSET              (XLEN-4)
 299 #define CSR_TDATA1_TYPE_LENGTH              4
 300 #define CSR_TDATA1_TYPE                     (0xfULL << CSR_TDATA1_TYPE_OFFSET)
 301 /*
 302 * 0: Both Debug and M Mode can write the {\tt tdata} registers at the
 303 * selected \Rtselect.
 304 *
 305 * 1: Only Debug Mode can write the {\tt tdata} registers at the
 306 * selected \Rtselect.  Writes from other modes are ignored.
 307 *
 308 * This bit is only writable from Debug Mode.
 309  */
 310 #define CSR_TDATA1_DMODE_OFFSET             (XLEN-5)
 311 #define CSR_TDATA1_DMODE_LENGTH             1
 312 #define CSR_TDATA1_DMODE                    (0x1ULL << CSR_TDATA1_DMODE_OFFSET)
 313 /*
 314 * Trigger-specific data.
 315  */
 316 #define CSR_TDATA1_DATA_OFFSET              0
 317 #define CSR_TDATA1_DATA_LENGTH              (XLEN - 5)
 318 #define CSR_TDATA1_DATA                     (((1L<<XLEN - 5)-1) << CSR_TDATA1_DATA_OFFSET)
 319 #define CSR_TDATA2                          0x7a2
 320 #define CSR_TDATA2_DATA_OFFSET              0
 321 #define CSR_TDATA2_DATA_LENGTH              XLEN
 322 #define CSR_TDATA2_DATA                     (((1L<<XLEN)-1) << CSR_TDATA2_DATA_OFFSET)
 323 #define CSR_TDATA3                          0x7a3
 324 #define CSR_TDATA3_DATA_OFFSET              0
 325 #define CSR_TDATA3_DATA_LENGTH              XLEN
 326 #define CSR_TDATA3_DATA                     (((1L<<XLEN)-1) << CSR_TDATA3_DATA_OFFSET)
 327 #define CSR_MCONTROL                        0x7a1
 328 #define CSR_MCONTROL_TYPE_OFFSET            (XLEN-4)
 329 #define CSR_MCONTROL_TYPE_LENGTH            4
 330 #define CSR_MCONTROL_TYPE                   (0xfULL << CSR_MCONTROL_TYPE_OFFSET)
 331 #define CSR_MCONTROL_DMODE_OFFSET           (XLEN-5)
 332 #define CSR_MCONTROL_DMODE_LENGTH           1
 333 #define CSR_MCONTROL_DMODE                  (0x1ULL << CSR_MCONTROL_DMODE_OFFSET)
 334 /*
 335 * Specifies the largest naturally aligned powers-of-two (NAPOT) range
 336 * supported by the hardware. The value is the logarithm base 2 of the
 337 * number of bytes in that range.  A value of 0 indicates that only
 338 * exact value matches are supported (one byte range). A value of 63
 339 * corresponds to the maximum NAPOT range, which is $2^{63}$ bytes in
 340 * size.
 341  */
 342 #define CSR_MCONTROL_MASKMAX_OFFSET         (XLEN-11)
 343 #define CSR_MCONTROL_MASKMAX_LENGTH         6
 344 #define CSR_MCONTROL_MASKMAX                (0x3fULL << CSR_MCONTROL_MASKMAX_OFFSET)
 345 /*
 346 * 0: Perform a match on the virtual address.
 347 *
 348 * 1: Perform a match on the data value loaded/stored, or the
 349 * instruction executed.
 350  */
 351 #define CSR_MCONTROL_SELECT_OFFSET          19
 352 #define CSR_MCONTROL_SELECT_LENGTH          1
 353 #define CSR_MCONTROL_SELECT                 (0x1ULL << CSR_MCONTROL_SELECT_OFFSET)
 354 /*
 355 * 0: The action for this trigger will be taken just before the
 356 * instruction that triggered it is executed, but after all preceding
 357 * instructions are are committed.
 358 *
 359 * 1: The action for this trigger will be taken after the instruction
 360 * that triggered it is executed. It should be taken before the next
 361 * instruction is executed, but it is better to implement triggers and
 362 * not implement that suggestion than to not implement them at all.
 363 *
 364 * Most hardware will only implement one timing or the other, possibly
 365 * dependent on \Fselect, \Fexecute, \Fload, and \Fstore. This bit
 366 * primarily exists for the hardware to communicate to the debugger
 367 * what will happen. Hardware may implement the bit fully writable, in
 368 * which case the debugger has a little more control.
 369 *
 370 * Data load triggers with \Ftiming of 0 will result in the same load
 371 * happening again when the debugger lets the core run. For data load
 372 * triggers, debuggers must first attempt to set the breakpoint with
 373 * \Ftiming of 1.
 374 *
 375 * A chain of triggers that don't all have the same \Ftiming value
 376 * will never fire (unless consecutive instructions match the
 377 * appropriate triggers).
 378  */
 379 #define CSR_MCONTROL_TIMING_OFFSET          18
 380 #define CSR_MCONTROL_TIMING_LENGTH          1
 381 #define CSR_MCONTROL_TIMING                 (0x1ULL << CSR_MCONTROL_TIMING_OFFSET)
 382 /*
 383 * Determines what happens when this trigger matches.
 384 *
 385 * 0: Raise a breakpoint exception. (Used when software wants to use
 386 * the trigger module without an external debugger attached.)
 387 *
 388 * 1: Enter Debug Mode. (Only supported when \Fdmode is 1.)
 389 *
 390 * 2: Start tracing.
 391 *
 392 * 3: Stop tracing.
 393 *
 394 * 4: Emit trace data for this match. If it is a data access match,
 395 * emit appropriate Load/Store Address/Data. If it is an instruction
 396 * execution, emit its PC.
 397 *
 398 * Other values are reserved for future use.
 399  */
 400 #define CSR_MCONTROL_ACTION_OFFSET          12
 401 #define CSR_MCONTROL_ACTION_LENGTH          6
 402 #define CSR_MCONTROL_ACTION                 (0x3fULL << CSR_MCONTROL_ACTION_OFFSET)
 403 /*
 404 * 0: When this trigger matches, the configured action is taken.
 405 *
 406 * 1: While this trigger does not match, it prevents the trigger with
 407 * the next index from matching.
 408  */
 409 #define CSR_MCONTROL_CHAIN_OFFSET           11
 410 #define CSR_MCONTROL_CHAIN_LENGTH           1
 411 #define CSR_MCONTROL_CHAIN                  (0x1ULL << CSR_MCONTROL_CHAIN_OFFSET)
 412 /*
 413 * 0: Matches when the value equals \Rtdatatwo.
 414 *
 415 * 1: Matches when the top M bits of the value match the top M bits of
 416 * \Rtdatatwo. M is XLEN-1 minus the index of the least-significant
 417 * bit containing 0 in \Rtdatatwo.
 418 *
 419 * 2: Matches when the value is greater than (unsigned) or equal to
 420 * \Rtdatatwo.
 421 *
 422 * 3: Matches when the value is less than (unsigned) \Rtdatatwo.
 423 *
 424 * 4: Matches when the lower half of the value equals the lower half
 425 * of \Rtdatatwo after the lower half of the value is ANDed with the
 426 * upper half of \Rtdatatwo.
 427 *
 428 * 5: Matches when the upper half of the value equals the lower half
 429 * of \Rtdatatwo after the upper half of the value is ANDed with the
 430 * upper half of \Rtdatatwo.
 431 *
 432 * Other values are reserved for future use.
 433  */
 434 #define CSR_MCONTROL_MATCH_OFFSET           7
 435 #define CSR_MCONTROL_MATCH_LENGTH           4
 436 #define CSR_MCONTROL_MATCH                  (0xfULL << CSR_MCONTROL_MATCH_OFFSET)
 437 /*
 438 * When set, enable this trigger in M mode.
 439  */
 440 #define CSR_MCONTROL_M_OFFSET               6
 441 #define CSR_MCONTROL_M_LENGTH               1
 442 #define CSR_MCONTROL_M                      (0x1ULL << CSR_MCONTROL_M_OFFSET)
 443 /*
 444 * When set, enable this trigger in H mode.
 445  */
 446 #define CSR_MCONTROL_H_OFFSET               5
 447 #define CSR_MCONTROL_H_LENGTH               1
 448 #define CSR_MCONTROL_H                      (0x1ULL << CSR_MCONTROL_H_OFFSET)
 449 /*
 450 * When set, enable this trigger in S mode.
 451  */
 452 #define CSR_MCONTROL_S_OFFSET               4
 453 #define CSR_MCONTROL_S_LENGTH               1
 454 #define CSR_MCONTROL_S                      (0x1ULL << CSR_MCONTROL_S_OFFSET)
 455 /*
 456 * When set, enable this trigger in U mode.
 457  */
 458 #define CSR_MCONTROL_U_OFFSET               3
 459 #define CSR_MCONTROL_U_LENGTH               1
 460 #define CSR_MCONTROL_U                      (0x1ULL << CSR_MCONTROL_U_OFFSET)
 461 /*
 462 * When set, the trigger fires on the virtual address or opcode of an
 463 * instruction that is executed.
 464  */
 465 #define CSR_MCONTROL_EXECUTE_OFFSET         2
 466 #define CSR_MCONTROL_EXECUTE_LENGTH         1
 467 #define CSR_MCONTROL_EXECUTE                (0x1ULL << CSR_MCONTROL_EXECUTE_OFFSET)
 468 /*
 469 * When set, the trigger fires on the virtual address or data of a store.
 470  */
 471 #define CSR_MCONTROL_STORE_OFFSET           1
 472 #define CSR_MCONTROL_STORE_LENGTH           1
 473 #define CSR_MCONTROL_STORE                  (0x1ULL << CSR_MCONTROL_STORE_OFFSET)
 474 /*
 475 * When set, the trigger fires on the virtual address or data of a load.
 476  */
 477 #define CSR_MCONTROL_LOAD_OFFSET            0
 478 #define CSR_MCONTROL_LOAD_LENGTH            1
 479 #define CSR_MCONTROL_LOAD                   (0x1ULL << CSR_MCONTROL_LOAD_OFFSET)
 480 #define CSR_ICOUNT                          0x7a1
 481 #define CSR_ICOUNT_TYPE_OFFSET              (XLEN-4)
 482 #define CSR_ICOUNT_TYPE_LENGTH              4
 483 #define CSR_ICOUNT_TYPE                     (0xfULL << CSR_ICOUNT_TYPE_OFFSET)
 484 #define CSR_ICOUNT_DMODE_OFFSET             (XLEN-5)
 485 #define CSR_ICOUNT_DMODE_LENGTH             1
 486 #define CSR_ICOUNT_DMODE                    (0x1ULL << CSR_ICOUNT_DMODE_OFFSET)
 487 /*
 488 * When count is decremented to 0, the trigger fires. Instead of
 489 * changing \Fcount from 1 to 0, it is also acceptable for hardware to
 490 * clear \Fm, \Fh, \Fs, and \Fu. This allows \Fcount to be hard-wired
 491 * to 1 if this register just exists for single step.
 492  */
 493 #define CSR_ICOUNT_COUNT_OFFSET             10
 494 #define CSR_ICOUNT_COUNT_LENGTH             14
 495 #define CSR_ICOUNT_COUNT                    (0x3fffULL << CSR_ICOUNT_COUNT_OFFSET)
 496 /*
 497 * When set, every instruction completed or exception taken in M mode decrements \Fcount
 498 * by 1.
 499  */
 500 #define CSR_ICOUNT_M_OFFSET                 9
 501 #define CSR_ICOUNT_M_LENGTH                 1
 502 #define CSR_ICOUNT_M                        (0x1ULL << CSR_ICOUNT_M_OFFSET)
 503 /*
 504 * When set, every instruction completed or exception taken in in H mode decrements \Fcount
 505 * by 1.
 506  */
 507 #define CSR_ICOUNT_H_OFFSET                 8
 508 #define CSR_ICOUNT_H_LENGTH                 1
 509 #define CSR_ICOUNT_H                        (0x1ULL << CSR_ICOUNT_H_OFFSET)
 510 /*
 511 * When set, every instruction completed or exception taken in S mode decrements \Fcount
 512 * by 1.
 513  */
 514 #define CSR_ICOUNT_S_OFFSET                 7
 515 #define CSR_ICOUNT_S_LENGTH                 1
 516 #define CSR_ICOUNT_S                        (0x1ULL << CSR_ICOUNT_S_OFFSET)
 517 /*
 518 * When set, every instruction completed or exception taken in U mode decrements \Fcount
 519 * by 1.
 520  */
 521 #define CSR_ICOUNT_U_OFFSET                 6
 522 #define CSR_ICOUNT_U_LENGTH                 1
 523 #define CSR_ICOUNT_U                        (0x1ULL << CSR_ICOUNT_U_OFFSET)
 524 /*
 525 * Determines what happens when this trigger matches.
 526 *
 527 * 0: Raise a breakpoint exception. (Used when software wants to use the
 528 * trigger module without an external debugger attached.)
 529 *
 530 * 1: Enter Debug Mode. (Only supported when \Fdmode is 1.)
 531 *
 532 * 2: Start tracing.
 533 *
 534 * 3: Stop tracing.
 535 *
 536 * 4: Emit trace data for this match. If it is a data access match,
 537 * emit appropriate Load/Store Address/Data. If it is an instruction
 538 * execution, emit its PC.
 539 *
 540 * Other values are reserved for future use.
 541  */
 542 #define CSR_ICOUNT_ACTION_OFFSET            0
 543 #define CSR_ICOUNT_ACTION_LENGTH            6
 544 #define CSR_ICOUNT_ACTION                   (0x3fULL << CSR_ICOUNT_ACTION_OFFSET)
 545 #define DMI_DMSTATUS                        0x11
 546 /*
 547 * Gets set if the Debug Module was accessed incorrectly.
 548 *
 549 * 0 (none): No error.
 550 *
 551 * 1 (badaddr): There was an access to an unimplemented Debug Module
 552 * address.
 553 *
 554 * 7 (other): An access failed for another reason.
 555  */
 556 #define DMI_DMSTATUS_DMERR_OFFSET           24
 557 #define DMI_DMSTATUS_DMERR_LENGTH           3
 558 #define DMI_DMSTATUS_DMERR                  (0x7U << DMI_DMSTATUS_DMERR_OFFSET)
 559 /*
 560 * If 1, then there is an implicit {\tt ebreak} instruction at the
 561 * non-existent word immediately after the Program Buffer. This saves
 562 * the debugger from having to write the {\tt ebreak} itself, and
 563 * allows the Program Buffer to be one word smaller.
 564 *
 565 * This must be 1 when \Fprogbufsize is 1.
 566  */
 567 #define DMI_DMSTATUS_IMPEBREAK_OFFSET       22
 568 #define DMI_DMSTATUS_IMPEBREAK_LENGTH       1
 569 #define DMI_DMSTATUS_IMPEBREAK              (0x1U << DMI_DMSTATUS_IMPEBREAK_OFFSET)
 570 /*
 571 * This field is 1 when all currently selected harts have been reset but the reset has not been acknowledged.
 572  */
 573 #define DMI_DMSTATUS_ALLHAVERESET_OFFSET    19
 574 #define DMI_DMSTATUS_ALLHAVERESET_LENGTH    1
 575 #define DMI_DMSTATUS_ALLHAVERESET           (0x1U << DMI_DMSTATUS_ALLHAVERESET_OFFSET)
 576 /*
 577 * This field is 1 when any currently selected hart has been reset but the reset has not been acknowledged.
 578  */
 579 #define DMI_DMSTATUS_ANYHAVERESET_OFFSET    18
 580 #define DMI_DMSTATUS_ANYHAVERESET_LENGTH    1
 581 #define DMI_DMSTATUS_ANYHAVERESET           (0x1U << DMI_DMSTATUS_ANYHAVERESET_OFFSET)
 582 /*
 583 * This field is 1 when all currently selected harts have acknowledged
 584 * the previous resume request.
 585  */
 586 #define DMI_DMSTATUS_ALLRESUMEACK_OFFSET    17
 587 #define DMI_DMSTATUS_ALLRESUMEACK_LENGTH    1
 588 #define DMI_DMSTATUS_ALLRESUMEACK           (0x1U << DMI_DMSTATUS_ALLRESUMEACK_OFFSET)
 589 /*
 590 * This field is 1 when any currently selected hart has acknowledged
 591 * the previous resume request.
 592  */
 593 #define DMI_DMSTATUS_ANYRESUMEACK_OFFSET    16
 594 #define DMI_DMSTATUS_ANYRESUMEACK_LENGTH    1
 595 #define DMI_DMSTATUS_ANYRESUMEACK           (0x1U << DMI_DMSTATUS_ANYRESUMEACK_OFFSET)
 596 /*
 597 * This field is 1 when all currently selected harts do not exist in this system.
 598  */
 599 #define DMI_DMSTATUS_ALLNONEXISTENT_OFFSET  15
 600 #define DMI_DMSTATUS_ALLNONEXISTENT_LENGTH  1
 601 #define DMI_DMSTATUS_ALLNONEXISTENT         (0x1U << DMI_DMSTATUS_ALLNONEXISTENT_OFFSET)
 602 /*
 603 * This field is 1 when any currently selected hart does not exist in this system.
 604  */
 605 #define DMI_DMSTATUS_ANYNONEXISTENT_OFFSET  14
 606 #define DMI_DMSTATUS_ANYNONEXISTENT_LENGTH  1
 607 #define DMI_DMSTATUS_ANYNONEXISTENT         (0x1U << DMI_DMSTATUS_ANYNONEXISTENT_OFFSET)
 608 /*
 609 * This field is 1 when all currently selected harts are unavailable.
 610  */
 611 #define DMI_DMSTATUS_ALLUNAVAIL_OFFSET      13
 612 #define DMI_DMSTATUS_ALLUNAVAIL_LENGTH      1
 613 #define DMI_DMSTATUS_ALLUNAVAIL             (0x1U << DMI_DMSTATUS_ALLUNAVAIL_OFFSET)
 614 /*
 615 * This field is 1 when any currently selected hart is unavailable.
 616  */
 617 #define DMI_DMSTATUS_ANYUNAVAIL_OFFSET      12
 618 #define DMI_DMSTATUS_ANYUNAVAIL_LENGTH      1
 619 #define DMI_DMSTATUS_ANYUNAVAIL             (0x1U << DMI_DMSTATUS_ANYUNAVAIL_OFFSET)
 620 /*
 621 * This field is 1 when all currently selected harts are running.
 622  */
 623 #define DMI_DMSTATUS_ALLRUNNING_OFFSET      11
 624 #define DMI_DMSTATUS_ALLRUNNING_LENGTH      1
 625 #define DMI_DMSTATUS_ALLRUNNING             (0x1U << DMI_DMSTATUS_ALLRUNNING_OFFSET)
 626 /*
 627 * This field is 1 when any currently selected hart is running.
 628  */
 629 #define DMI_DMSTATUS_ANYRUNNING_OFFSET      10
 630 #define DMI_DMSTATUS_ANYRUNNING_LENGTH      1
 631 #define DMI_DMSTATUS_ANYRUNNING             (0x1U << DMI_DMSTATUS_ANYRUNNING_OFFSET)
 632 /*
 633 * This field is 1 when all currently selected harts are halted.
 634  */
 635 #define DMI_DMSTATUS_ALLHALTED_OFFSET       9
 636 #define DMI_DMSTATUS_ALLHALTED_LENGTH       1
 637 #define DMI_DMSTATUS_ALLHALTED              (0x1U << DMI_DMSTATUS_ALLHALTED_OFFSET)
 638 /*
 639 * This field is 1 when any currently selected hart is halted.
 640  */
 641 #define DMI_DMSTATUS_ANYHALTED_OFFSET       8
 642 #define DMI_DMSTATUS_ANYHALTED_LENGTH       1
 643 #define DMI_DMSTATUS_ANYHALTED              (0x1U << DMI_DMSTATUS_ANYHALTED_OFFSET)
 644 /*
 645 * 0 when authentication is required before using the DM.  1 when the
 646 * authentication check has passed. On components that don't implement
 647 * authentication, this bit must be preset as 1.
 648  */
 649 #define DMI_DMSTATUS_AUTHENTICATED_OFFSET   7
 650 #define DMI_DMSTATUS_AUTHENTICATED_LENGTH   1
 651 #define DMI_DMSTATUS_AUTHENTICATED          (0x1U << DMI_DMSTATUS_AUTHENTICATED_OFFSET)
 652 /*
 653 * 0: The authentication module is ready to process the next
 654 * read/write to \Rauthdata.
 655 *
 656 * 1: The authentication module is busy. Accessing \Rauthdata results
 657 * in unspecified behavior.
 658 *
 659 * \Fauthbusy only becomes set in immediate response to an access to
 660 * \Rauthdata.
 661  */
 662 #define DMI_DMSTATUS_AUTHBUSY_OFFSET        6
 663 #define DMI_DMSTATUS_AUTHBUSY_LENGTH        1
 664 #define DMI_DMSTATUS_AUTHBUSY               (0x1U << DMI_DMSTATUS_AUTHBUSY_OFFSET)
 665 /*
 666 * 0: \Rdevtreeaddrzero--\Rdevtreeaddrthree hold information which
 667 * is not relevant to the Device Tree.
 668 *
 669 * 1: \Rdevtreeaddrzero--\Rdevtreeaddrthree registers hold the address of the
 670 * Device Tree.
 671  */
 672 #define DMI_DMSTATUS_DEVTREEVALID_OFFSET    4
 673 #define DMI_DMSTATUS_DEVTREEVALID_LENGTH    1
 674 #define DMI_DMSTATUS_DEVTREEVALID           (0x1U << DMI_DMSTATUS_DEVTREEVALID_OFFSET)
 675 /*
 676 * 0: There is no Debug Module present.
 677 *
 678 * 1: There is a Debug Module and it conforms to version 0.11 of this
 679 * specification.
 680 *
 681 * 2: There is a Debug Module and it conforms to version 0.13 of this
 682 * specification.
 683 *
 684 * 15: There is a Debug Module but it does not conform to any
 685 * available version of this spec.
 686  */
 687 #define DMI_DMSTATUS_VERSION_OFFSET         0
 688 #define DMI_DMSTATUS_VERSION_LENGTH         4
 689 #define DMI_DMSTATUS_VERSION                (0xfU << DMI_DMSTATUS_VERSION_OFFSET)
 690 #define DMI_DMCONTROL                       0x10
 691 /*
 692 * Writes the halt request bit for all currently selected harts.
 693 * When set to 1, each selected hart will halt if it is not currently
 694 * halted.
 695 *
 696 * Writing 1 or 0 has no effect on a hart which is already halted, but
 697 * the bit must be cleared to 0 before the hart is resumed.
 698 *
 699 * Writes apply to the new value of \Fhartsel and \Fhasel.
 700  */
 701 #define DMI_DMCONTROL_HALTREQ_OFFSET        31
 702 #define DMI_DMCONTROL_HALTREQ_LENGTH        1
 703 #define DMI_DMCONTROL_HALTREQ               (0x1U << DMI_DMCONTROL_HALTREQ_OFFSET)
 704 /*
 705 * Writes the resume request bit for all currently selected harts.
 706 * When set to 1, each selected hart will resume if it is currently
 707 * halted.
 708 *
 709 * The resume request bit is ignored while the halt request bit is
 710 * set.
 711 *
 712 * Writes apply to the new value of \Fhartsel and \Fhasel.
 713  */
 714 #define DMI_DMCONTROL_RESUMEREQ_OFFSET      30
 715 #define DMI_DMCONTROL_RESUMEREQ_LENGTH      1
 716 #define DMI_DMCONTROL_RESUMEREQ             (0x1U << DMI_DMCONTROL_RESUMEREQ_OFFSET)
 717 /*
 718 * This optional field writes the reset bit for all the currently
 719 * selected harts.  To perform a reset the debugger writes 1, and then
 720 * writes 0 to deassert the reset signal.
 721 *
 722 * If this feature is not implemented, the bit always stays 0, so
 723 * after writing 1 the debugger can read the register back to see if
 724 * the feature is supported.
 725 *
 726 * Writes apply to the new value of \Fhartsel and \Fhasel.
 727  */
 728 #define DMI_DMCONTROL_HARTRESET_OFFSET      29
 729 #define DMI_DMCONTROL_HARTRESET_LENGTH      1
 730 #define DMI_DMCONTROL_HARTRESET             (0x1U << DMI_DMCONTROL_HARTRESET_OFFSET)
 731 /*
 732 * Writing 1 to this bit clears the {\tt havereset} bits for
 733 * any selected harts.
 734 *
 735 * Writes apply to the new value of \Fhartsel and \Fhasel.
 736  */
 737 #define DMI_DMCONTROL_ACKHAVERESET_OFFSET   28
 738 #define DMI_DMCONTROL_ACKHAVERESET_LENGTH   1
 739 #define DMI_DMCONTROL_ACKHAVERESET          (0x1U << DMI_DMCONTROL_ACKHAVERESET_OFFSET)
 740 /*
 741 * Selects the  definition of currently selected harts.
 742 *
 743 * 0: There is a single currently selected hart, that selected by \Fhartsel.
 744 *
 745 * 1: There may be multiple currently selected harts -- that selected by \Fhartsel,
 746 * plus those selected by the hart array mask register.
 747 *
 748 * An implementation which does not implement the hart array mask register
 749 * should tie this field to 0. A debugger which wishes to use the hart array
 750 * mask register feature should set this bit and read back to see if the functionality
 751 * is supported.
 752  */
 753 #define DMI_DMCONTROL_HASEL_OFFSET          26
 754 #define DMI_DMCONTROL_HASEL_LENGTH          1
 755 #define DMI_DMCONTROL_HASEL                 (0x1U << DMI_DMCONTROL_HASEL_OFFSET)
 756 /*
 757 * The DM-specific index of the hart to select. This hart is always part of the
 758 * currently selected harts.
 759  */
 760 #define DMI_DMCONTROL_HARTSEL_OFFSET        16
 761 #define DMI_DMCONTROL_HARTSEL_LENGTH        10
 762 #define DMI_DMCONTROL_HARTSEL               (0x3ffU << DMI_DMCONTROL_HARTSEL_OFFSET)
 763 /*
 764 * This bit controls the reset signal from the DM to the rest of the
 765 * system. The signal should reset every part of the system, including
 766 * every hart, except for the DM and any logic required to access the
 767 * DM.
 768 * To perform a system reset the debugger writes 1,
 769 * and then writes 0
 770 * to deassert the reset.
 771  */
 772 #define DMI_DMCONTROL_NDMRESET_OFFSET       1
 773 #define DMI_DMCONTROL_NDMRESET_LENGTH       1
 774 #define DMI_DMCONTROL_NDMRESET              (0x1U << DMI_DMCONTROL_NDMRESET_OFFSET)
 775 /*
 776 * This bit serves as a reset signal for the Debug Module itself.
 777 *
 778 * 0: The module's state, including authentication mechanism,
 779 * takes its reset values (the \Fdmactive bit is the only bit which can
 780 * be written to something other than its reset value).
 781 *
 782 * 1: The module functions normally.
 783 *
 784 * No other mechanism should exist that may result in resetting the
 785 * Debug Module after power up, including the platform's system reset
 786 * or Debug Transport reset signals.
 787 *
 788 * A debugger may pulse this bit low to get the debug module into a
 789 * known state.
 790 *
 791 * Implementations may use this bit to aid debugging, for example by
 792 * preventing the Debug Module from being power gated while debugging
 793 * is active.
 794  */
 795 #define DMI_DMCONTROL_DMACTIVE_OFFSET       0
 796 #define DMI_DMCONTROL_DMACTIVE_LENGTH       1
 797 #define DMI_DMCONTROL_DMACTIVE              (0x1U << DMI_DMCONTROL_DMACTIVE_OFFSET)
 798 #define DMI_HARTINFO                        0x12
 799 /*
 800 * Number of {\tt dscratch} registers available for the debugger
 801 * to use during program buffer execution, starting from \Rdscratchzero.
 802 * The debugger can make no assumptions about the contents of these
 803 * registers between commands.
 804  */
 805 #define DMI_HARTINFO_NSCRATCH_OFFSET        20
 806 #define DMI_HARTINFO_NSCRATCH_LENGTH        4
 807 #define DMI_HARTINFO_NSCRATCH               (0xfU << DMI_HARTINFO_NSCRATCH_OFFSET)
 808 /*
 809 * 0: The {\tt data} registers are shadowed in the hart by CSR
 810 * registers. Each CSR register is XLEN bits in size, and corresponds
 811 * to a single argument, per Table~\ref{tab:datareg}.
 812 *
 813 * 1: The {\tt data} registers are shadowed in the hart's memory map.
 814 * Each register takes up 4 bytes in the memory map.
 815  */
 816 #define DMI_HARTINFO_DATAACCESS_OFFSET      16
 817 #define DMI_HARTINFO_DATAACCESS_LENGTH      1
 818 #define DMI_HARTINFO_DATAACCESS             (0x1U << DMI_HARTINFO_DATAACCESS_OFFSET)
 819 /*
 820 * If \Fdataaccess is 0: Number of CSR registers dedicated to
 821 * shadowing the {\tt data} registers.
 822 *
 823 * If \Fdataaccess is 1: Number of 32-bit words in the memory map
 824 * dedicated to shadowing the {\tt data} registers.
 825  */
 826 #define DMI_HARTINFO_DATASIZE_OFFSET        12
 827 #define DMI_HARTINFO_DATASIZE_LENGTH        4
 828 #define DMI_HARTINFO_DATASIZE               (0xfU << DMI_HARTINFO_DATASIZE_OFFSET)
 829 /*
 830 * If \Fdataaccess is 0: The number of the first CSR dedicated to
 831 * shadowing the {\tt data} registers.
 832 *
 833 * If \Fdataaccess is 1: Signed address of RAM where the {\tt data}
 834 * registers are shadowed, to be used to access relative to \Rzero.
 835  */
 836 #define DMI_HARTINFO_DATAADDR_OFFSET        0
 837 #define DMI_HARTINFO_DATAADDR_LENGTH        12
 838 #define DMI_HARTINFO_DATAADDR               (0xfffU << DMI_HARTINFO_DATAADDR_OFFSET)
 839 #define DMI_HALTSUM                         0x13
 840 #define DMI_HALTSUM_HALT1023_992_OFFSET     31
 841 #define DMI_HALTSUM_HALT1023_992_LENGTH     1
 842 #define DMI_HALTSUM_HALT1023_992            (0x1U << DMI_HALTSUM_HALT1023_992_OFFSET)
 843 #define DMI_HALTSUM_HALT991_960_OFFSET      30
 844 #define DMI_HALTSUM_HALT991_960_LENGTH      1
 845 #define DMI_HALTSUM_HALT991_960             (0x1U << DMI_HALTSUM_HALT991_960_OFFSET)
 846 #define DMI_HALTSUM_HALT959_928_OFFSET      29
 847 #define DMI_HALTSUM_HALT959_928_LENGTH      1
 848 #define DMI_HALTSUM_HALT959_928             (0x1U << DMI_HALTSUM_HALT959_928_OFFSET)
 849 #define DMI_HALTSUM_HALT927_896_OFFSET      28
 850 #define DMI_HALTSUM_HALT927_896_LENGTH      1
 851 #define DMI_HALTSUM_HALT927_896             (0x1U << DMI_HALTSUM_HALT927_896_OFFSET)
 852 #define DMI_HALTSUM_HALT895_864_OFFSET      27
 853 #define DMI_HALTSUM_HALT895_864_LENGTH      1
 854 #define DMI_HALTSUM_HALT895_864             (0x1U << DMI_HALTSUM_HALT895_864_OFFSET)
 855 #define DMI_HALTSUM_HALT863_832_OFFSET      26
 856 #define DMI_HALTSUM_HALT863_832_LENGTH      1
 857 #define DMI_HALTSUM_HALT863_832             (0x1U << DMI_HALTSUM_HALT863_832_OFFSET)
 858 #define DMI_HALTSUM_HALT831_800_OFFSET      25
 859 #define DMI_HALTSUM_HALT831_800_LENGTH      1
 860 #define DMI_HALTSUM_HALT831_800             (0x1U << DMI_HALTSUM_HALT831_800_OFFSET)
 861 #define DMI_HALTSUM_HALT799_768_OFFSET      24
 862 #define DMI_HALTSUM_HALT799_768_LENGTH      1
 863 #define DMI_HALTSUM_HALT799_768             (0x1U << DMI_HALTSUM_HALT799_768_OFFSET)
 864 #define DMI_HALTSUM_HALT767_736_OFFSET      23
 865 #define DMI_HALTSUM_HALT767_736_LENGTH      1
 866 #define DMI_HALTSUM_HALT767_736             (0x1U << DMI_HALTSUM_HALT767_736_OFFSET)
 867 #define DMI_HALTSUM_HALT735_704_OFFSET      22
 868 #define DMI_HALTSUM_HALT735_704_LENGTH      1
 869 #define DMI_HALTSUM_HALT735_704             (0x1U << DMI_HALTSUM_HALT735_704_OFFSET)
 870 #define DMI_HALTSUM_HALT703_672_OFFSET      21
 871 #define DMI_HALTSUM_HALT703_672_LENGTH      1
 872 #define DMI_HALTSUM_HALT703_672             (0x1U << DMI_HALTSUM_HALT703_672_OFFSET)
 873 #define DMI_HALTSUM_HALT671_640_OFFSET      20
 874 #define DMI_HALTSUM_HALT671_640_LENGTH      1
 875 #define DMI_HALTSUM_HALT671_640             (0x1U << DMI_HALTSUM_HALT671_640_OFFSET)
 876 #define DMI_HALTSUM_HALT639_608_OFFSET      19
 877 #define DMI_HALTSUM_HALT639_608_LENGTH      1
 878 #define DMI_HALTSUM_HALT639_608             (0x1U << DMI_HALTSUM_HALT639_608_OFFSET)
 879 #define DMI_HALTSUM_HALT607_576_OFFSET      18
 880 #define DMI_HALTSUM_HALT607_576_LENGTH      1
 881 #define DMI_HALTSUM_HALT607_576             (0x1U << DMI_HALTSUM_HALT607_576_OFFSET)
 882 #define DMI_HALTSUM_HALT575_544_OFFSET      17
 883 #define DMI_HALTSUM_HALT575_544_LENGTH      1
 884 #define DMI_HALTSUM_HALT575_544             (0x1U << DMI_HALTSUM_HALT575_544_OFFSET)
 885 #define DMI_HALTSUM_HALT543_512_OFFSET      16
 886 #define DMI_HALTSUM_HALT543_512_LENGTH      1
 887 #define DMI_HALTSUM_HALT543_512             (0x1U << DMI_HALTSUM_HALT543_512_OFFSET)
 888 #define DMI_HALTSUM_HALT511_480_OFFSET      15
 889 #define DMI_HALTSUM_HALT511_480_LENGTH      1
 890 #define DMI_HALTSUM_HALT511_480             (0x1U << DMI_HALTSUM_HALT511_480_OFFSET)
 891 #define DMI_HALTSUM_HALT479_448_OFFSET      14
 892 #define DMI_HALTSUM_HALT479_448_LENGTH      1
 893 #define DMI_HALTSUM_HALT479_448             (0x1U << DMI_HALTSUM_HALT479_448_OFFSET)
 894 #define DMI_HALTSUM_HALT447_416_OFFSET      13
 895 #define DMI_HALTSUM_HALT447_416_LENGTH      1
 896 #define DMI_HALTSUM_HALT447_416             (0x1U << DMI_HALTSUM_HALT447_416_OFFSET)
 897 #define DMI_HALTSUM_HALT415_384_OFFSET      12
 898 #define DMI_HALTSUM_HALT415_384_LENGTH      1
 899 #define DMI_HALTSUM_HALT415_384             (0x1U << DMI_HALTSUM_HALT415_384_OFFSET)
 900 #define DMI_HALTSUM_HALT383_352_OFFSET      11
 901 #define DMI_HALTSUM_HALT383_352_LENGTH      1
 902 #define DMI_HALTSUM_HALT383_352             (0x1U << DMI_HALTSUM_HALT383_352_OFFSET)
 903 #define DMI_HALTSUM_HALT351_320_OFFSET      10
 904 #define DMI_HALTSUM_HALT351_320_LENGTH      1
 905 #define DMI_HALTSUM_HALT351_320             (0x1U << DMI_HALTSUM_HALT351_320_OFFSET)
 906 #define DMI_HALTSUM_HALT319_288_OFFSET      9
 907 #define DMI_HALTSUM_HALT319_288_LENGTH      1
 908 #define DMI_HALTSUM_HALT319_288             (0x1U << DMI_HALTSUM_HALT319_288_OFFSET)
 909 #define DMI_HALTSUM_HALT287_256_OFFSET      8
 910 #define DMI_HALTSUM_HALT287_256_LENGTH      1
 911 #define DMI_HALTSUM_HALT287_256             (0x1U << DMI_HALTSUM_HALT287_256_OFFSET)
 912 #define DMI_HALTSUM_HALT255_224_OFFSET      7
 913 #define DMI_HALTSUM_HALT255_224_LENGTH      1
 914 #define DMI_HALTSUM_HALT255_224             (0x1U << DMI_HALTSUM_HALT255_224_OFFSET)
 915 #define DMI_HALTSUM_HALT223_192_OFFSET      6
 916 #define DMI_HALTSUM_HALT223_192_LENGTH      1
 917 #define DMI_HALTSUM_HALT223_192             (0x1U << DMI_HALTSUM_HALT223_192_OFFSET)
 918 #define DMI_HALTSUM_HALT191_160_OFFSET      5
 919 #define DMI_HALTSUM_HALT191_160_LENGTH      1
 920 #define DMI_HALTSUM_HALT191_160             (0x1U << DMI_HALTSUM_HALT191_160_OFFSET)
 921 #define DMI_HALTSUM_HALT159_128_OFFSET      4
 922 #define DMI_HALTSUM_HALT159_128_LENGTH      1
 923 #define DMI_HALTSUM_HALT159_128             (0x1U << DMI_HALTSUM_HALT159_128_OFFSET)
 924 #define DMI_HALTSUM_HALT127_96_OFFSET       3
 925 #define DMI_HALTSUM_HALT127_96_LENGTH       1
 926 #define DMI_HALTSUM_HALT127_96              (0x1U << DMI_HALTSUM_HALT127_96_OFFSET)
 927 #define DMI_HALTSUM_HALT95_64_OFFSET        2
 928 #define DMI_HALTSUM_HALT95_64_LENGTH        1
 929 #define DMI_HALTSUM_HALT95_64               (0x1U << DMI_HALTSUM_HALT95_64_OFFSET)
 930 #define DMI_HALTSUM_HALT63_32_OFFSET        1
 931 #define DMI_HALTSUM_HALT63_32_LENGTH        1
 932 #define DMI_HALTSUM_HALT63_32               (0x1U << DMI_HALTSUM_HALT63_32_OFFSET)
 933 #define DMI_HALTSUM_HALT31_0_OFFSET         0
 934 #define DMI_HALTSUM_HALT31_0_LENGTH         1
 935 #define DMI_HALTSUM_HALT31_0                (0x1U << DMI_HALTSUM_HALT31_0_OFFSET)
 936 #define DMI_HAWINDOWSEL                     0x14
 937 #define DMI_HAWINDOWSEL_HAWINDOWSEL_OFFSET  0
 938 #define DMI_HAWINDOWSEL_HAWINDOWSEL_LENGTH  5
 939 #define DMI_HAWINDOWSEL_HAWINDOWSEL         (0x1fU << DMI_HAWINDOWSEL_HAWINDOWSEL_OFFSET)
 940 #define DMI_HAWINDOW                        0x15
 941 #define DMI_HAWINDOW_MASKDATA_OFFSET        0
 942 #define DMI_HAWINDOW_MASKDATA_LENGTH        32
 943 #define DMI_HAWINDOW_MASKDATA               (0xffffffffU << DMI_HAWINDOW_MASKDATA_OFFSET)
 944 #define DMI_ABSTRACTCS                      0x16
 945 /*
 946 * Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 16.
 947  */
 948 #define DMI_ABSTRACTCS_PROGBUFSIZE_OFFSET   24
 949 #define DMI_ABSTRACTCS_PROGBUFSIZE_LENGTH   5
 950 #define DMI_ABSTRACTCS_PROGBUFSIZE          (0x1fU << DMI_ABSTRACTCS_PROGBUFSIZE_OFFSET)
 951 /*
 952 * 1: An abstract command is currently being executed.
 953 *
 954 * This bit is set as soon as \Rcommand is written, and is
 955 * not cleared until that command has completed.
 956  */
 957 #define DMI_ABSTRACTCS_BUSY_OFFSET          12
 958 #define DMI_ABSTRACTCS_BUSY_LENGTH          1
 959 #define DMI_ABSTRACTCS_BUSY                 (0x1U << DMI_ABSTRACTCS_BUSY_OFFSET)
 960 /*
 961 * Gets set if an abstract command fails. The bits in this field remain set until
 962 * they are cleared by writing 1 to them. No abstract command is
 963 * started until the value is reset to 0.
 964 *
 965 * 0 (none): No error.
 966 *
 967 * 1 (busy): An abstract command was executing while \Rcommand,
 968 * \Rabstractcs, \Rabstractauto was written, or when one
 969 * of the {\tt data} or {\tt progbuf} registers was read or written.
 970 *
 971 * 2 (not supported): The requested command is not supported. A
 972 * command that is not supported while the hart is running may be
 973 * supported when it is halted.
 974 *
 975 * 3 (exception): An exception occurred while executing the command
 976 * (eg. while executing the Program Buffer).
 977 *
 978 * 4 (halt/resume): An abstract command couldn't execute because the
 979 * hart wasn't in the expected state (running/halted).
 980 *
 981 * 7 (other): The command failed for another reason.
 982  */
 983 #define DMI_ABSTRACTCS_CMDERR_OFFSET        8
 984 #define DMI_ABSTRACTCS_CMDERR_LENGTH        3
 985 #define DMI_ABSTRACTCS_CMDERR               (0x7U << DMI_ABSTRACTCS_CMDERR_OFFSET)
 986 /*
 987 * Number of {\tt data} registers that are implemented as part of the
 988 * abstract command interface. Valid sizes are 0 - 12.
 989  */
 990 #define DMI_ABSTRACTCS_DATACOUNT_OFFSET     0
 991 #define DMI_ABSTRACTCS_DATACOUNT_LENGTH     5
 992 #define DMI_ABSTRACTCS_DATACOUNT            (0x1fU << DMI_ABSTRACTCS_DATACOUNT_OFFSET)
 993 #define DMI_COMMAND                         0x17
 994 /*
 995 * The type determines the overall functionality of this
 996 * abstract command.
 997  */
 998 #define DMI_COMMAND_CMDTYPE_OFFSET          24
 999 #define DMI_COMMAND_CMDTYPE_LENGTH          8
1000 #define DMI_COMMAND_CMDTYPE                 (0xffU << DMI_COMMAND_CMDTYPE_OFFSET)
1001 /*
1002 * This field is interpreted in a command-specific manner,
1003 * described for each abstract command.
1004  */
1005 #define DMI_COMMAND_CONTROL_OFFSET          0
1006 #define DMI_COMMAND_CONTROL_LENGTH          24
1007 #define DMI_COMMAND_CONTROL                 (0xffffffU << DMI_COMMAND_CONTROL_OFFSET)
1008 #define DMI_ABSTRACTAUTO                    0x18
1009 /*
1010 * When a bit in this field is 1, read or write accesses to the corresponding {\tt progbuf} word
1011 * cause the command in \Rcommand to be executed again.
1012  */
1013 #define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET 16
1014 #define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_LENGTH 16
1015 #define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF    (0xffffU << DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET)
1016 /*
1017 * When a bit in this field is 1, read or write accesses to the corresponding {\tt data} word
1018 * cause the command in \Rcommand to be executed again.
1019  */
1020 #define DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET 0
1021 #define DMI_ABSTRACTAUTO_AUTOEXECDATA_LENGTH 12
1022 #define DMI_ABSTRACTAUTO_AUTOEXECDATA       (0xfffU << DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET)
1023 #define DMI_DEVTREEADDR0                    0x19
1024 #define DMI_DEVTREEADDR0_ADDR_OFFSET        0
1025 #define DMI_DEVTREEADDR0_ADDR_LENGTH        32
1026 #define DMI_DEVTREEADDR0_ADDR               (0xffffffffU << DMI_DEVTREEADDR0_ADDR_OFFSET)
1027 #define DMI_DEVTREEADDR1                    0x1a
1028 #define DMI_DEVTREEADDR2                    0x1b
1029 #define DMI_DEVTREEADDR3                    0x1c
1030 #define DMI_DATA0                           0x04
1031 #define DMI_DATA0_DATA_OFFSET               0
1032 #define DMI_DATA0_DATA_LENGTH               32
1033 #define DMI_DATA0_DATA                      (0xffffffffU << DMI_DATA0_DATA_OFFSET)
1034 #define DMI_DATA11                          0x0f
1035 #define DMI_PROGBUF0                        0x20
1036 #define DMI_PROGBUF0_DATA_OFFSET            0
1037 #define DMI_PROGBUF0_DATA_LENGTH            32
1038 #define DMI_PROGBUF0_DATA                   (0xffffffffU << DMI_PROGBUF0_DATA_OFFSET)
1039 #define DMI_PROGBUF15                       0x2f
1040 #define DMI_AUTHDATA                        0x30
1041 #define DMI_AUTHDATA_DATA_OFFSET            0
1042 #define DMI_AUTHDATA_DATA_LENGTH            32
1043 #define DMI_AUTHDATA_DATA                   (0xffffffffU << DMI_AUTHDATA_DATA_OFFSET)
1044 #define DMI_SBADDRESS3                      0x37
1045 /*
1046 * Accesses bits 127:96 of the physical address in {\tt sbaddress} (if
1047 * the system address bus is that wide).
1048  */
1049 #define DMI_SBADDRESS3_ADDRESS_OFFSET       0
1050 #define DMI_SBADDRESS3_ADDRESS_LENGTH       32
1051 #define DMI_SBADDRESS3_ADDRESS              (0xffffffffU << DMI_SBADDRESS3_ADDRESS_OFFSET)
1052 #define DMI_SBCS                            0x38
1053 /*
1054 * 0: The System Bus interface conforms to mainline drafts of this
1055 * spec older than 1 January, 2018.
1056 *
1057 * 1: The System Bus interface conforms to this version of the spec.
1058 *
1059 * Other values are reserved for future versions.
1060  */
1061 #define DMI_SBCS_VERSION_OFFSET             29
1062 #define DMI_SBCS_VERSION_LENGTH             3
1063 #define DMI_SBCS_VERSION                    (0x7U << DMI_SBCS_VERSION_OFFSET)
1064 /*
1065 * When a 1, every write to \Rsbaddresszero automatically triggers a
1066 * system bus read at the new address.
1067  */
1068 #define DMI_SBCS_SBREADONADDR_OFFSET        20
1069 #define DMI_SBCS_SBREADONADDR_LENGTH        1
1070 #define DMI_SBCS_SBREADONADDR               (0x1U << DMI_SBCS_SBREADONADDR_OFFSET)
1071 /*
1072 * Select the access size to use for system bus accesses triggered by
1073 * writes to \Rsbaddresszero or \Rsbdatazero.
1074 *
1075 * 0: 8-bit
1076 *
1077 * 1: 16-bit
1078 *
1079 * 2: 32-bit
1080 *
1081 * 3: 64-bit
1082 *
1083 * 4: 128-bit
1084 *
1085 * If an unsupported system bus access size is written here, the DM
1086 * does not perform the access and sberror is set to 3.
1087  */
1088 #define DMI_SBCS_SBACCESS_OFFSET            17
1089 #define DMI_SBCS_SBACCESS_LENGTH            3
1090 #define DMI_SBCS_SBACCESS                   (0x7U << DMI_SBCS_SBACCESS_OFFSET)
1091 /*
1092 * When 1, {\tt sbaddress} is incremented by the access size (in
1093 * bytes) selected in \Fsbaccess after every system bus access.
1094  */
1095 #define DMI_SBCS_SBAUTOINCREMENT_OFFSET     16
1096 #define DMI_SBCS_SBAUTOINCREMENT_LENGTH     1
1097 #define DMI_SBCS_SBAUTOINCREMENT            (0x1U << DMI_SBCS_SBAUTOINCREMENT_OFFSET)
1098 /*
1099 * When 1, every read from \Rsbdatazero automatically triggers a
1100 * system bus read at the (possibly auto-incremented) address.
1101  */
1102 #define DMI_SBCS_SBREADONDATA_OFFSET        15
1103 #define DMI_SBCS_SBREADONDATA_LENGTH        1
1104 #define DMI_SBCS_SBREADONDATA               (0x1U << DMI_SBCS_SBREADONDATA_OFFSET)
1105 /*
1106 * When the debug module's system bus
1107 * master causes a bus error, this field gets set. The bits in this
1108 * field remain set until they are cleared by writing 1 to them.
1109 * While this field is non-zero, no more system bus accesses can be
1110 * initiated by the debug module.
1111 *
1112 * 0: There was no bus error.
1113 *
1114 * 1: There was a timeout.
1115 *
1116 * 2: A bad address was accessed.
1117 *
1118 * 3: There was some other error (eg. alignment).
1119 *
1120 * 4: The system bus master was busy when one of the
1121 * {\tt sbaddress} or {\tt sbdata} registers was written,
1122 * or \Rsbdatazero was read when it had stale data.
1123  */
1124 #define DMI_SBCS_SBERROR_OFFSET             12
1125 #define DMI_SBCS_SBERROR_LENGTH             3
1126 #define DMI_SBCS_SBERROR                    (0x7U << DMI_SBCS_SBERROR_OFFSET)
1127 /*
1128 * Width of system bus addresses in bits. (0 indicates there is no bus
1129 * access support.)
1130  */
1131 #define DMI_SBCS_SBASIZE_OFFSET             5
1132 #define DMI_SBCS_SBASIZE_LENGTH             7
1133 #define DMI_SBCS_SBASIZE                    (0x7fU << DMI_SBCS_SBASIZE_OFFSET)
1134 /*
1135 * 1 when 128-bit system bus accesses are supported.
1136  */
1137 #define DMI_SBCS_SBACCESS128_OFFSET         4
1138 #define DMI_SBCS_SBACCESS128_LENGTH         1
1139 #define DMI_SBCS_SBACCESS128                (0x1U << DMI_SBCS_SBACCESS128_OFFSET)
1140 /*
1141 * 1 when 64-bit system bus accesses are supported.
1142  */
1143 #define DMI_SBCS_SBACCESS64_OFFSET          3
1144 #define DMI_SBCS_SBACCESS64_LENGTH          1
1145 #define DMI_SBCS_SBACCESS64                 (0x1U << DMI_SBCS_SBACCESS64_OFFSET)
1146 /*
1147 * 1 when 32-bit system bus accesses are supported.
1148  */
1149 #define DMI_SBCS_SBACCESS32_OFFSET          2
1150 #define DMI_SBCS_SBACCESS32_LENGTH          1
1151 #define DMI_SBCS_SBACCESS32                 (0x1U << DMI_SBCS_SBACCESS32_OFFSET)
1152 /*
1153 * 1 when 16-bit system bus accesses are supported.
1154  */
1155 #define DMI_SBCS_SBACCESS16_OFFSET          1
1156 #define DMI_SBCS_SBACCESS16_LENGTH          1
1157 #define DMI_SBCS_SBACCESS16                 (0x1U << DMI_SBCS_SBACCESS16_OFFSET)
1158 /*
1159 * 1 when 8-bit system bus accesses are supported.
1160  */
1161 #define DMI_SBCS_SBACCESS8_OFFSET           0
1162 #define DMI_SBCS_SBACCESS8_LENGTH           1
1163 #define DMI_SBCS_SBACCESS8                  (0x1U << DMI_SBCS_SBACCESS8_OFFSET)
1164 #define DMI_SBADDRESS0                      0x39
1165 /*
1166 * Accesses bits 31:0 of the physical address in {\tt sbaddress}.
1167  */
1168 #define DMI_SBADDRESS0_ADDRESS_OFFSET       0
1169 #define DMI_SBADDRESS0_ADDRESS_LENGTH       32
1170 #define DMI_SBADDRESS0_ADDRESS              (0xffffffffU << DMI_SBADDRESS0_ADDRESS_OFFSET)
1171 #define DMI_SBADDRESS1                      0x3a
1172 /*
1173 * Accesses bits 63:32 of the physical address in {\tt sbaddress} (if
1174 * the system address bus is that wide).
1175  */
1176 #define DMI_SBADDRESS1_ADDRESS_OFFSET       0
1177 #define DMI_SBADDRESS1_ADDRESS_LENGTH       32
1178 #define DMI_SBADDRESS1_ADDRESS              (0xffffffffU << DMI_SBADDRESS1_ADDRESS_OFFSET)
1179 #define DMI_SBADDRESS2                      0x3b
1180 /*
1181 * Accesses bits 95:64 of the physical address in {\tt sbaddress} (if
1182 * the system address bus is that wide).
1183  */
1184 #define DMI_SBADDRESS2_ADDRESS_OFFSET       0
1185 #define DMI_SBADDRESS2_ADDRESS_LENGTH       32
1186 #define DMI_SBADDRESS2_ADDRESS              (0xffffffffU << DMI_SBADDRESS2_ADDRESS_OFFSET)
1187 #define DMI_SBDATA0                         0x3c
1188 /*
1189 * Accesses bits 31:0 of {\tt sbdata}.
1190  */
1191 #define DMI_SBDATA0_DATA_OFFSET             0
1192 #define DMI_SBDATA0_DATA_LENGTH             32
1193 #define DMI_SBDATA0_DATA                    (0xffffffffU << DMI_SBDATA0_DATA_OFFSET)
1194 #define DMI_SBDATA1                         0x3d
1195 /*
1196 * Accesses bits 63:32 of {\tt sbdata} (if the system bus is that
1197 * wide).
1198  */
1199 #define DMI_SBDATA1_DATA_OFFSET             0
1200 #define DMI_SBDATA1_DATA_LENGTH             32
1201 #define DMI_SBDATA1_DATA                    (0xffffffffU << DMI_SBDATA1_DATA_OFFSET)
1202 #define DMI_SBDATA2                         0x3e
1203 /*
1204 * Accesses bits 95:64 of {\tt sbdata} (if the system bus is that
1205 * wide).
1206  */
1207 #define DMI_SBDATA2_DATA_OFFSET             0
1208 #define DMI_SBDATA2_DATA_LENGTH             32
1209 #define DMI_SBDATA2_DATA                    (0xffffffffU << DMI_SBDATA2_DATA_OFFSET)
1210 #define DMI_SBDATA3                         0x3f
1211 /*
1212 * Accesses bits 127:96 of {\tt sbdata} (if the system bus is that
1213 * wide).
1214  */
1215 #define DMI_SBDATA3_DATA_OFFSET             0
1216 #define DMI_SBDATA3_DATA_LENGTH             32
1217 #define DMI_SBDATA3_DATA                    (0xffffffffU << DMI_SBDATA3_DATA_OFFSET)
1218 #define SHORTNAME                           0x123
1219 /*
1220 * Description of what this field is used for.
1221  */
1222 #define SHORTNAME_FIELD_OFFSET              0
1223 #define SHORTNAME_FIELD_LENGTH              8
1224 #define SHORTNAME_FIELD                     (0xffU << SHORTNAME_FIELD_OFFSET)
1225 #define AC_ACCESS_REGISTER                  None
1226 /*
1227 * This is 0 to indicate Access Register Command.
1228  */
1229 #define AC_ACCESS_REGISTER_CMDTYPE_OFFSET   24
1230 #define AC_ACCESS_REGISTER_CMDTYPE_LENGTH   8
1231 #define AC_ACCESS_REGISTER_CMDTYPE          (0xffU << AC_ACCESS_REGISTER_CMDTYPE_OFFSET)
1232 /*
1233 * 2: Access the lowest 32 bits of the register.
1234 *
1235 * 3: Access the lowest 64 bits of the register.
1236 *
1237 * 4: Access the lowest 128 bits of the register.
1238 *
1239 * If \Fsize specifies a size larger than the register's actual size,
1240 * then the access must fail. If a register is accessible, then reads of \Fsize
1241 * less than or equal to the register's actual size must be supported.
1242  */
1243 #define AC_ACCESS_REGISTER_SIZE_OFFSET      20
1244 #define AC_ACCESS_REGISTER_SIZE_LENGTH      3
1245 #define AC_ACCESS_REGISTER_SIZE             (0x7U << AC_ACCESS_REGISTER_SIZE_OFFSET)
1246 /*
1247 * When 1, execute the program in the Program Buffer exactly once
1248 * after performing the transfer, if any.
1249  */
1250 #define AC_ACCESS_REGISTER_POSTEXEC_OFFSET  18
1251 #define AC_ACCESS_REGISTER_POSTEXEC_LENGTH  1
1252 #define AC_ACCESS_REGISTER_POSTEXEC         (0x1U << AC_ACCESS_REGISTER_POSTEXEC_OFFSET)
1253 /*
1254 * 0: Don't do the operation specified by \Fwrite.
1255 *
1256 * 1: Do the operation specified by \Fwrite.
1257 *
1258 * This bit can be used to just execute the Program Buffer without
1259 * having to worry about placing valid values into \Fsize or \Fregno.
1260  */
1261 #define AC_ACCESS_REGISTER_TRANSFER_OFFSET  17
1262 #define AC_ACCESS_REGISTER_TRANSFER_LENGTH  1
1263 #define AC_ACCESS_REGISTER_TRANSFER         (0x1U << AC_ACCESS_REGISTER_TRANSFER_OFFSET)
1264 /*
1265 * When \Ftransfer is set:
1266 * 0: Copy data from the specified register into {\tt arg0} portion
1267 * of {\tt data}.
1268 *
1269 * 1: Copy data from {\tt arg0} portion of {\tt data} into the
1270 * specified register.
1271  */
1272 #define AC_ACCESS_REGISTER_WRITE_OFFSET     16
1273 #define AC_ACCESS_REGISTER_WRITE_LENGTH     1
1274 #define AC_ACCESS_REGISTER_WRITE            (0x1U << AC_ACCESS_REGISTER_WRITE_OFFSET)
1275 /*
1276 * Number of the register to access, as described in
1277 * Table~\ref{tab:regno}.
1278 * \Rdpc may be used as an alias for PC if this command is
1279 * supported on a non-halted hart.
1280  */
1281 #define AC_ACCESS_REGISTER_REGNO_OFFSET     0
1282 #define AC_ACCESS_REGISTER_REGNO_LENGTH     16
1283 #define AC_ACCESS_REGISTER_REGNO            (0xffffU << AC_ACCESS_REGISTER_REGNO_OFFSET)
1284 #define AC_QUICK_ACCESS                     None
1285 /*
1286 * This is 1 to indicate Quick Access command.
1287  */
1288 #define AC_QUICK_ACCESS_CMDTYPE_OFFSET      24
1289 #define AC_QUICK_ACCESS_CMDTYPE_LENGTH      8
1290 #define AC_QUICK_ACCESS_CMDTYPE             (0xffU << AC_QUICK_ACCESS_CMDTYPE_OFFSET)
1291 #define VIRT_PRIV                           virtual
1292 /*
1293 * Contains the privilege level the hart was operating in when Debug
1294 * Mode was entered. The encoding is described in Table
1295 * \ref{tab:privlevel}, and matches the privilege level encoding from
1296 * the RISC-V Privileged ISA Specification. A user can write this
1297 * value to change the hart's privilege level when exiting Debug Mode.
1298  */
1299 #define VIRT_PRIV_PRV_OFFSET                0
1300 #define VIRT_PRIV_PRV_LENGTH                2
1301 #define VIRT_PRIV_PRV                       (0x3U << VIRT_PRIV_PRV_OFFSET)
1302 #define DMI_SERCS                           0x34
1303 /*
1304 * Number of supported serial ports.
1305  */
1306 #define DMI_SERCS_SERIALCOUNT_OFFSET        28
1307 #define DMI_SERCS_SERIALCOUNT_LENGTH        4
1308 #define DMI_SERCS_SERIALCOUNT               (0xfU << DMI_SERCS_SERIALCOUNT_OFFSET)
1309 /*
1310 * Select which serial port is accessed by \Rserrx and \Rsertx.
1311  */
1312 #define DMI_SERCS_SERIAL_OFFSET             24
1313 #define DMI_SERCS_SERIAL_LENGTH             3
1314 #define DMI_SERCS_SERIAL                    (0x7U << DMI_SERCS_SERIAL_OFFSET)
1315 #define DMI_SERCS_ERROR7_OFFSET             23
1316 #define DMI_SERCS_ERROR7_LENGTH             1
1317 #define DMI_SERCS_ERROR7                    (0x1U << DMI_SERCS_ERROR7_OFFSET)
1318 #define DMI_SERCS_VALID7_OFFSET             22
1319 #define DMI_SERCS_VALID7_LENGTH             1
1320 #define DMI_SERCS_VALID7                    (0x1U << DMI_SERCS_VALID7_OFFSET)
1321 #define DMI_SERCS_FULL7_OFFSET              21
1322 #define DMI_SERCS_FULL7_LENGTH              1
1323 #define DMI_SERCS_FULL7                     (0x1U << DMI_SERCS_FULL7_OFFSET)
1324 #define DMI_SERCS_ERROR6_OFFSET             20
1325 #define DMI_SERCS_ERROR6_LENGTH             1
1326 #define DMI_SERCS_ERROR6                    (0x1U << DMI_SERCS_ERROR6_OFFSET)
1327 #define DMI_SERCS_VALID6_OFFSET             19
1328 #define DMI_SERCS_VALID6_LENGTH             1
1329 #define DMI_SERCS_VALID6                    (0x1U << DMI_SERCS_VALID6_OFFSET)
1330 #define DMI_SERCS_FULL6_OFFSET              18
1331 #define DMI_SERCS_FULL6_LENGTH              1
1332 #define DMI_SERCS_FULL6                     (0x1U << DMI_SERCS_FULL6_OFFSET)
1333 #define DMI_SERCS_ERROR5_OFFSET             17
1334 #define DMI_SERCS_ERROR5_LENGTH             1
1335 #define DMI_SERCS_ERROR5                    (0x1U << DMI_SERCS_ERROR5_OFFSET)
1336 #define DMI_SERCS_VALID5_OFFSET             16
1337 #define DMI_SERCS_VALID5_LENGTH             1
1338 #define DMI_SERCS_VALID5                    (0x1U << DMI_SERCS_VALID5_OFFSET)
1339 #define DMI_SERCS_FULL5_OFFSET              15
1340 #define DMI_SERCS_FULL5_LENGTH              1
1341 #define DMI_SERCS_FULL5                     (0x1U << DMI_SERCS_FULL5_OFFSET)
1342 #define DMI_SERCS_ERROR4_OFFSET             14
1343 #define DMI_SERCS_ERROR4_LENGTH             1
1344 #define DMI_SERCS_ERROR4                    (0x1U << DMI_SERCS_ERROR4_OFFSET)
1345 #define DMI_SERCS_VALID4_OFFSET             13
1346 #define DMI_SERCS_VALID4_LENGTH             1
1347 #define DMI_SERCS_VALID4                    (0x1U << DMI_SERCS_VALID4_OFFSET)
1348 #define DMI_SERCS_FULL4_OFFSET              12
1349 #define DMI_SERCS_FULL4_LENGTH              1
1350 #define DMI_SERCS_FULL4                     (0x1U << DMI_SERCS_FULL4_OFFSET)
1351 #define DMI_SERCS_ERROR3_OFFSET             11
1352 #define DMI_SERCS_ERROR3_LENGTH             1
1353 #define DMI_SERCS_ERROR3                    (0x1U << DMI_SERCS_ERROR3_OFFSET)
1354 #define DMI_SERCS_VALID3_OFFSET             10
1355 #define DMI_SERCS_VALID3_LENGTH             1
1356 #define DMI_SERCS_VALID3                    (0x1U << DMI_SERCS_VALID3_OFFSET)
1357 #define DMI_SERCS_FULL3_OFFSET              9
1358 #define DMI_SERCS_FULL3_LENGTH              1
1359 #define DMI_SERCS_FULL3                     (0x1U << DMI_SERCS_FULL3_OFFSET)
1360 #define DMI_SERCS_ERROR2_OFFSET             8
1361 #define DMI_SERCS_ERROR2_LENGTH             1
1362 #define DMI_SERCS_ERROR2                    (0x1U << DMI_SERCS_ERROR2_OFFSET)
1363 #define DMI_SERCS_VALID2_OFFSET             7
1364 #define DMI_SERCS_VALID2_LENGTH             1
1365 #define DMI_SERCS_VALID2                    (0x1U << DMI_SERCS_VALID2_OFFSET)
1366 #define DMI_SERCS_FULL2_OFFSET              6
1367 #define DMI_SERCS_FULL2_LENGTH              1
1368 #define DMI_SERCS_FULL2                     (0x1U << DMI_SERCS_FULL2_OFFSET)
1369 #define DMI_SERCS_ERROR1_OFFSET             5
1370 #define DMI_SERCS_ERROR1_LENGTH             1
1371 #define DMI_SERCS_ERROR1                    (0x1U << DMI_SERCS_ERROR1_OFFSET)
1372 #define DMI_SERCS_VALID1_OFFSET             4
1373 #define DMI_SERCS_VALID1_LENGTH             1
1374 #define DMI_SERCS_VALID1                    (0x1U << DMI_SERCS_VALID1_OFFSET)
1375 #define DMI_SERCS_FULL1_OFFSET              3
1376 #define DMI_SERCS_FULL1_LENGTH              1
1377 #define DMI_SERCS_FULL1                     (0x1U << DMI_SERCS_FULL1_OFFSET)
1378 /*
1379 * 1 when the debugger-to-core queue for serial port 0 has
1380 * over or underflowed. This bit will remain set until it is reset by
1381 * writing 1 to this bit.
1382  */
1383 #define DMI_SERCS_ERROR0_OFFSET             2
1384 #define DMI_SERCS_ERROR0_LENGTH             1
1385 #define DMI_SERCS_ERROR0                    (0x1U << DMI_SERCS_ERROR0_OFFSET)
1386 /*
1387 * 1 when the core-to-debugger queue for serial port 0 is not empty.
1388  */
1389 #define DMI_SERCS_VALID0_OFFSET             1
1390 #define DMI_SERCS_VALID0_LENGTH             1
1391 #define DMI_SERCS_VALID0                    (0x1U << DMI_SERCS_VALID0_OFFSET)
1392 /*
1393 * 1 when the debugger-to-core queue for serial port 0 is full.
1394  */
1395 #define DMI_SERCS_FULL0_OFFSET              0
1396 #define DMI_SERCS_FULL0_LENGTH              1
1397 #define DMI_SERCS_FULL0                     (0x1U << DMI_SERCS_FULL0_OFFSET)
1398 #define DMI_SERTX                           0x35
1399 #define DMI_SERTX_DATA_OFFSET               0
1400 #define DMI_SERTX_DATA_LENGTH               32
1401 #define DMI_SERTX_DATA                      (0xffffffffU << DMI_SERTX_DATA_OFFSET)
1402 #define DMI_SERRX                           0x36
1403 #define DMI_SERRX_DATA_OFFSET               0
1404 #define DMI_SERRX_DATA_LENGTH               32
1405 #define DMI_SERRX_DATA                      (0xffffffffU << DMI_SERRX_DATA_OFFSET)