riscv/debug_module.h

   1 // See LICENSE for license details.
   2 #ifndef _RISCV_DEBUG_MODULE_H
   3 #define _RISCV_DEBUG_MODULE_H
   4
   5 #include <set>
   6
   7 #include "devices.h"
   8
   9 class sim_t;
  10
  11 typedef struct {
  12   bool haltreq;
  13   bool resumereq;
  14   unsigned hartsel;
  15   bool hartreset;
  16   bool dmactive;
  17   bool ndmreset;
  18 } dmcontrol_t;
  19
  20 typedef struct {
  21   bool impebreak;
  22   bool allnonexistant;
  23   bool anynonexistant;
  24   bool allunavail;
  25   bool anyunavail;
  26   bool allrunning;
  27   bool anyrunning;
  28   bool allhalted;
  29   bool anyhalted;
  30   bool allresumeack;
  31   bool anyresumeack;
  32   bool authenticated;
  33   bool authbusy;
  34   bool cfgstrvalid;
  35   unsigned version;
  36 } dmstatus_t;
  37
  38 typedef enum cmderr {
  39     CMDERR_NONE = 0,
  40     CMDERR_BUSY = 1,
  41     CMDERR_NOTSUP = 2,
  42     CMDERR_EXCEPTION = 3,
  43     CMDERR_HALTRESUME = 4,
  44     CMDERR_OTHER = 7
  45 } cmderr_t;
  46
  47 typedef struct {
  48   bool busy;
  49   unsigned datacount;
  50   unsigned progbufsize;
  51   cmderr_t cmderr;
  52 } abstractcs_t;
  53
  54 typedef struct {
  55   unsigned autoexecprogbuf;
  56   unsigned autoexecdata;
  57 } abstractauto_t;
  58
  59 typedef struct {
  60   unsigned version;
  61   bool readonaddr;
  62   unsigned sbaccess;
  63   bool autoincrement;
  64   bool readondata;
  65   unsigned error;
  66   unsigned asize;
  67   bool access128;
  68   bool access64;
  69   bool access32;
  70   bool access16;
  71   bool access8;
  72 } sbcs_t;
  73
  74 class debug_module_t : public abstract_device_t
  75 {
  76   public:
  77     debug_module_t(sim_t *sim, unsigned progbufsize, unsigned max_bus_master_bits);
  78     ~debug_module_t();
  79
  80     void add_device(bus_t *bus);
  81
  82     bool load(reg_t addr, size_t len, uint8_t* bytes);
  83     bool store(reg_t addr, size_t len, const uint8_t* bytes);
  84
  85     // Debug Module Interface that the debugger (in our case through JTAG DTM)
  86     // uses to access the DM.
  87     // Return true for success, false for failure.
  88     bool dmi_read(unsigned address, uint32_t *value);
  89     bool dmi_write(unsigned address, uint32_t value);
  90
  91   private:
  92     static const unsigned datasize = 2;
  93     // Size of program_buffer in 32-bit words, as exposed to the rest of the
  94     // world.
  95     unsigned progbufsize;
  96     // Actual size of the program buffer, which is 1 word bigger than we let on
  97     // to implement the implicit ebreak at the end.
  98     unsigned program_buffer_bytes;
  99     unsigned max_bus_master_bits ;
 100     static const unsigned debug_data_start = 0x380;
 101     unsigned debug_progbuf_start;
 102
 103     static const unsigned debug_abstract_size = 2;
 104     unsigned debug_abstract_start;
 105
 106     static const unsigned hartsellen = 10;
 107
 108     sim_t *sim;
 109
 110     uint8_t debug_rom_whereto[4];
 111     uint8_t debug_abstract[debug_abstract_size * 4];
 112     uint8_t *program_buffer;
 113     uint8_t dmdata[datasize * 4];
 114
 115     bool halted[1024];
 116     bool resumeack[1024];
 117     uint8_t debug_rom_flags[1024];
 118
 119     void write32(uint8_t *rom, unsigned int index, uint32_t value);
 120     uint32_t read32(uint8_t *rom, unsigned int index);
 121
 122     void sb_autoincrement();
 123     void sb_read();
 124     void sb_write();
 125     unsigned sb_access_bits();
 126
 127     dmcontrol_t dmcontrol;
 128     dmstatus_t dmstatus;
 129     abstractcs_t abstractcs;
 130     abstractauto_t abstractauto;
 131     uint32_t command;
 132
 133     sbcs_t sbcs;
 134     uint32_t sbaddress[4];
 135     uint32_t sbdata[4];
 136
 137     processor_t *current_proc() const;
 138     void reset();
 139     bool perform_abstract_command();
 140 };
 141
 142 #endif