riscv/decode.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_DECODE_H
   4 #define _RISCV_DECODE_H
   5
   6 #if (-1 != ~0) || ((-1 >> 1) != -1)
   7 # error spike requires a two''s-complement c++ implementation
   8 #endif
   9
  10 #ifdef WORDS_BIGENDIAN
  11 # error spike requires a little-endian host
  12 #endif
  13
  14 #include <cstdint>
  15 #include <string.h>
  16 #include <strings.h>
  17 #include "encoding.h"
  18 #include "config.h"
  19 #include "common.h"
  20 #include "softfloat_types.h"
  21 #include "specialize.h"
  22 #include <cinttypes>
  23
  24 typedef int64_t sreg_t;
  25 typedef uint64_t reg_t;
  26
  27 const int NXPR = 32;
  28 const int NFPR = 32;
  29 const int NCSR = 4096;
  30
  31 #define X_RA 1
  32 #define X_SP 2
  33
  34 #define FP_RD_NE  0
  35 #define FP_RD_0   1
  36 #define FP_RD_DN  2
  37 #define FP_RD_UP  3
  38 #define FP_RD_NMM 4
  39
  40 #define FSR_RD_SHIFT 5
  41 #define FSR_RD   (0x7 << FSR_RD_SHIFT)
  42
  43 #define FPEXC_NX 0x01
  44 #define FPEXC_UF 0x02
  45 #define FPEXC_OF 0x04
  46 #define FPEXC_DZ 0x08
  47 #define FPEXC_NV 0x10
  48
  49 #define FSR_AEXC_SHIFT 0
  50 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
  51 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
  52 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
  53 #define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)
  54 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
  55 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  56
  57 #define insn_length(x) \
  58   (((x) & 0x03) < 0x03 ? 2 : \
  59    ((x) & 0x1f) < 0x1f ? 4 : \
  60    ((x) & 0x3f) < 0x3f ? 6 : \
  61    8)
  62 #define MAX_INSN_LENGTH 8
  63 #define PC_ALIGN 2
  64
  65 typedef uint64_t insn_bits_t;
  66 class insn_t
  67 {
  68 public:
  69   insn_t() = default;
  70   insn_t(insn_bits_t bits) : b(bits) {}
  71   insn_bits_t bits() { return b; }
  72   int length() { return insn_length(b); }
  73   int64_t i_imm() { return int64_t(b) >> 20; }
  74   int64_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); }
  75   int64_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); }
  76   int64_t u_imm() { return int64_t(b) >> 12 << 12; }
  77   int64_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); }
  78   uint64_t rd() { return x(7, 5); }
  79   uint64_t rs1() { return x(15, 5); }
  80   uint64_t rs2() { return x(20, 5); }
  81   uint64_t rs3() { return x(27, 5); }
  82   uint64_t rm() { return x(12, 3); }
  83   uint64_t csr() { return x(20, 12); }
  84
  85   int64_t rvc_imm() { return x(2, 5) + (xs(12, 1) << 5); }
  86   int64_t rvc_zimm() { return x(2, 5) + (x(12, 1) << 5); }
  87   int64_t rvc_addi4spn_imm() { return (x(6, 1) << 2) + (x(5, 1) << 3) + (x(11, 2) << 4) + (x(7, 4) << 6); }
  88   int64_t rvc_addi16sp_imm() { return (x(6, 1) << 4) + (x(2, 1) << 5) + (x(5, 1) << 6) + (x(3, 2) << 7) + (xs(12, 1) << 9); }
  89   int64_t rvc_lwsp_imm() { return (x(4, 3) << 2) + (x(12, 1) << 5) + (x(2, 2) << 6); }
  90   int64_t rvc_ldsp_imm() { return (x(5, 2) << 3) + (x(12, 1) << 5) + (x(2, 3) << 6); }
  91   int64_t rvc_swsp_imm() { return (x(9, 4) << 2) + (x(7, 2) << 6); }
  92   int64_t rvc_sdsp_imm() { return (x(10, 3) << 3) + (x(7, 3) << 6); }
  93   int64_t rvc_lw_imm() { return (x(6, 1) << 2) + (x(10, 3) << 3) + (x(5, 1) << 6); }
  94   int64_t rvc_ld_imm() { return (x(10, 3) << 3) + (x(5, 2) << 6); }
  95   int64_t rvc_j_imm() { return (x(3, 3) << 1) + (x(11, 1) << 4) + (x(2, 1) << 5) + (x(7, 1) << 6) + (x(6, 1) << 7) + (x(9, 2) << 8) + (x(8, 1) << 10) + (xs(12, 1) << 11); }
  96   int64_t rvc_b_imm() { return (x(3, 2) << 1) + (x(10, 2) << 3) + (x(2, 1) << 5) + (x(5, 2) << 6) + (xs(12, 1) << 8); }
  97   int64_t rvc_simm3() { return x(10, 3); }
  98   uint64_t rvc_rd() { return rd(); }
  99   uint64_t rvc_rs1() { return rd(); }
 100   uint64_t rvc_rs2() { return x(2, 5); }
 101   uint64_t rvc_rs1s() { return 8 + x(7, 3); }
 102   uint64_t rvc_rs2s() { return 8 + x(2, 3); }
 103 private:
 104   insn_bits_t b;
 105   uint64_t x(int lo, int len) { return (b >> lo) & ((insn_bits_t(1) << len)-1); }
 106   uint64_t xs(int lo, int len) { return int64_t(b) << (64-lo-len) >> (64-len); }
 107   uint64_t imm_sign() { return xs(63, 1); }
 108 };
 109
 110 template <class T, size_t N, bool zero_reg>
 111 class regfile_t
 112 {
 113 public:
 114   void write(size_t i, T value)
 115   {
 116     if (!zero_reg || i != 0)
 117       data[i] = value;
 118   }
 119   const T& operator [] (size_t i) const
 120   {
 121     return data[i];
 122   }
 123 private:
 124   T data[N];
 125 };
 126
 127 // helpful macros, etc
 128 #define MMU (*p->get_mmu())
 129 #define STATE (*p->get_state())
 130 #define READ_REG(reg) STATE.XPR[reg]
 131 #define READ_FREG(reg) STATE.FPR[reg]
 132 #define RS1 READ_REG(insn.rs1())
 133 #define RS2 READ_REG(insn.rs2())
 134 #define WRITE_RD(value) WRITE_REG(insn.rd(), value)
 135
 136 #ifndef RISCV_ENABLE_COMMITLOG
 137 # define WRITE_REG(reg, value) STATE.XPR.write(reg, value)
 138 # define WRITE_FREG(reg, value) DO_WRITE_FREG(reg, freg(value))
 139 #else
 140 # define WRITE_REG(reg, value) ({ \
 141     reg_t wdata = (value); /* value may have side effects */ \
 142     STATE.log_reg_write = (commit_log_reg_t){(reg) << 1, {wdata, 0}}; \
 143     STATE.XPR.write(reg, wdata); \
 144   })
 145 # define WRITE_FREG(reg, value) ({ \
 146     freg_t wdata = freg(value); /* value may have side effects */ \
 147     STATE.log_reg_write = (commit_log_reg_t){((reg) << 1) | 1, wdata}; \
 148     DO_WRITE_FREG(reg, wdata); \
 149   })
 150 #endif
 151
 152 // RVC macros
 153 #define WRITE_RVC_RS1S(value) WRITE_REG(insn.rvc_rs1s(), value)
 154 #define WRITE_RVC_RS2S(value) WRITE_REG(insn.rvc_rs2s(), value)
 155 #define WRITE_RVC_FRS2S(value) WRITE_FREG(insn.rvc_rs2s(), value)
 156 #define RVC_RS1 READ_REG(insn.rvc_rs1())
 157 #define RVC_RS2 READ_REG(insn.rvc_rs2())
 158 #define RVC_RS1S READ_REG(insn.rvc_rs1s())
 159 #define RVC_RS2S READ_REG(insn.rvc_rs2s())
 160 #define RVC_FRS2 READ_FREG(insn.rvc_rs2())
 161 #define RVC_FRS2S READ_FREG(insn.rvc_rs2s())
 162 #define RVC_SP READ_REG(X_SP)
 163
 164 // FPU macros
 165 #define FRS1 READ_FREG(insn.rs1())
 166 #define FRS2 READ_FREG(insn.rs2())
 167 #define FRS3 READ_FREG(insn.rs3())
 168 #define dirty_fp_state (STATE.mstatus |= MSTATUS_FS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))
 169 #define dirty_ext_state (STATE.mstatus |= MSTATUS_XS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))
 170 #define DO_WRITE_FREG(reg, value) (STATE.FPR.write(reg, value), dirty_fp_state)
 171 #define WRITE_FRD(value) WRITE_FREG(insn.rd(), value)
 172
 173 #define SHAMT (insn.i_imm() & 0x3F)
 174 #define BRANCH_TARGET (pc + insn.sb_imm())
 175 #define JUMP_TARGET (pc + insn.uj_imm())
 176 #define RM ({ int rm = insn.rm(); \
 177               if(rm == 7) rm = STATE.frm; \
 178               if(rm > 4) throw trap_illegal_instruction(0); \
 179               rm; })
 180
 181 #define get_field(reg, mask) (((reg) & (decltype(reg))(mask)) / ((mask) & ~((mask) << 1)))
 182 #define set_field(reg, mask, val) (((reg) & ~(decltype(reg))(mask)) | (((decltype(reg))(val) * ((mask) & ~((mask) << 1))) & (decltype(reg))(mask)))
 183
 184 #define require(x) if (unlikely(!(x))) throw trap_illegal_instruction(0)
 185 #define require_privilege(p) require(STATE.prv >= (p))
 186 #define require_rv64 require(xlen == 64)
 187 #define require_rv32 require(xlen == 32)
 188 #define require_extension(s) require(p->supports_extension(s))
 189 #define require_fp require((STATE.mstatus & MSTATUS_FS) != 0)
 190 #define require_accelerator require((STATE.mstatus & MSTATUS_XS) != 0)
 191
 192 #define set_fp_exceptions ({ if (softfloat_exceptionFlags) { \
 193                                dirty_fp_state; \
 194                                STATE.fflags |= softfloat_exceptionFlags; \
 195                              } \
 196                              softfloat_exceptionFlags = 0; })
 197
 198 #define sext32(x) ((sreg_t)(int32_t)(x))
 199 #define zext32(x) ((reg_t)(uint32_t)(x))
 200 #define sext_xlen(x) (((sreg_t)(x) << (64-xlen)) >> (64-xlen))
 201 #define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen))
 202
 203 #define set_pc(x) \
 204   do { if (unlikely(((x) & 2)) && !p->supports_extension('C')) \
 205          throw trap_instruction_address_misaligned(x); \
 206        npc = sext_xlen(x); \
 207      } while(0)
 208
 209 #define set_pc_and_serialize(x) \
 210   do { reg_t __npc = (x); \
 211        set_pc(__npc); /* check alignment */ \
 212        npc = PC_SERIALIZE_AFTER; \
 213        STATE.pc = __npc; \
 214      } while(0)
 215
 216 /* Sentinel PC values to serialize simulator pipeline */
 217 #define PC_SERIALIZE_BEFORE 3
 218 #define PC_SERIALIZE_AFTER 5
 219 #define invalid_pc(pc) ((pc) & 1)
 220
 221 /* Convenience wrappers to simplify softfloat code sequences */
 222 #define isBoxedF32(r) (isBoxedF64(r) && ((uint32_t)((r.v[0] >> 32) + 1) == 0))
 223 #define unboxF32(r) (isBoxedF32(r) ? (uint32_t)r.v[0] : defaultNaNF32UI)
 224 #define isBoxedF64(r) ((r.v[1] + 1) == 0)
 225 #define unboxF64(r) (isBoxedF64(r) ? r.v[0] : defaultNaNF64UI)
 226 typedef float128_t freg_t;
 227 inline float32_t f32(uint32_t v) { return { v }; }
 228 inline float64_t f64(uint64_t v) { return { v }; }
 229 inline float32_t f32(freg_t r) { return f32(unboxF32(r)); }
 230 inline float64_t f64(freg_t r) { return f64(unboxF64(r)); }
 231 inline float128_t f128(freg_t r) { return r; }
 232 inline freg_t freg(float32_t f) { return { ((uint64_t)-1 << 32) | f.v, (uint64_t)-1 }; }
 233 inline freg_t freg(float64_t f) { return { f.v, (uint64_t)-1 }; }
 234 inline freg_t freg(float128_t f) { return f; }
 235 #define F32_SIGN ((uint32_t)1 << 31)
 236 #define F64_SIGN ((uint64_t)1 << 63)
 237 #define fsgnj32(a, b, n, x) \
 238   f32((f32(a).v & ~F32_SIGN) | ((((x) ? f32(a).v : (n) ? F32_SIGN : 0) ^ f32(b).v) & F32_SIGN))
 239 #define fsgnj64(a, b, n, x) \
 240   f64((f64(a).v & ~F64_SIGN) | ((((x) ? f64(a).v : (n) ? F64_SIGN : 0) ^ f64(b).v) & F64_SIGN))
 241
 242 #define isNaNF128(x) isNaNF128UI(x.v[1], x.v[0])
 243 inline float128_t defaultNaNF128()
 244 {
 245   float128_t nan;
 246   nan.v[1] = defaultNaNF128UI64;
 247   nan.v[0] = defaultNaNF128UI0;
 248   return nan;
 249 }
 250 inline freg_t fsgnj128(freg_t a, freg_t b, bool n, bool x)
 251 {
 252   a.v[1] = (a.v[1] & ~F64_SIGN) | (((x ? a.v[1] : n ? F64_SIGN : 0) ^ b.v[1]) & F64_SIGN);
 253   return a;
 254 }
 255 inline freg_t f128_negate(freg_t a)
 256 {
 257   a.v[1] ^= F64_SIGN;
 258   return a;
 259 }
 260
 261 #define validate_csr(which, write) ({ \
 262   if (!STATE.serialized) return PC_SERIALIZE_BEFORE; \
 263   STATE.serialized = false; \
 264   unsigned csr_priv = get_field((which), 0x300); \
 265   unsigned csr_read_only = get_field((which), 0xC00) == 3; \
 266   if (((write) && csr_read_only) || STATE.prv < csr_priv) \
 267     throw trap_illegal_instruction(0); \
 268   (which); })
 269
 270 // Seems that 0x0 doesn't work.
 271 #define DEBUG_START             0x100
 272 #define DEBUG_END                 (0x1000 - 1)
 273
 274 #endif