riscv/decode.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_DECODE_H
   4 #define _RISCV_DECODE_H
   5
   6 #if (-1 != ~0) || ((-1 >> 1) != -1)
   7 # error spike requires a two''s-complement c++ implementation
   8 #endif
   9
  10 #include <cstdint>
  11 #include <string.h>
  12 #include <strings.h>
  13 #include "encoding.h"
  14 #include "config.h"
  15 #include "common.h"
  16 #include <cinttypes>
  17
  18 typedef int64_t sreg_t;
  19 typedef uint64_t reg_t;
  20 typedef uint64_t freg_t;
  21
  22 const int NXPR = 32;
  23 const int NFPR = 32;
  24
  25 #define X_RA 1
  26 #define X_SP 2
  27
  28 #define FP_RD_NE  0
  29 #define FP_RD_0   1
  30 #define FP_RD_DN  2
  31 #define FP_RD_UP  3
  32 #define FP_RD_NMM 4
  33
  34 #define FSR_RD_SHIFT 5
  35 #define FSR_RD   (0x7 << FSR_RD_SHIFT)
  36
  37 #define FPEXC_NX 0x01
  38 #define FPEXC_UF 0x02
  39 #define FPEXC_OF 0x04
  40 #define FPEXC_DZ 0x08
  41 #define FPEXC_NV 0x10
  42
  43 #define FSR_AEXC_SHIFT 0
  44 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
  45 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
  46 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
  47 #define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)
  48 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
  49 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  50
  51 #define insn_length(x) \
  52   (((x) & 0x03) < 0x03 ? 2 : \
  53    ((x) & 0x1f) < 0x1f ? 4 : \
  54    ((x) & 0x3f) < 0x3f ? 6 : \
  55    8)
  56 #define MAX_INSN_LENGTH 8
  57 #define PC_ALIGN 2
  58
  59 typedef uint64_t insn_bits_t;
  60 class insn_t
  61 {
  62 public:
  63   insn_t() = default;
  64   insn_t(insn_bits_t bits) : b(bits) {}
  65   insn_bits_t bits() { return b; }
  66   int length() { return insn_length(b); }
  67   int64_t i_imm() { return int64_t(b) >> 20; }
  68   int64_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); }
  69   int64_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); }
  70   int64_t u_imm() { return int64_t(b) >> 12 << 12; }
  71   int64_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); }
  72   uint64_t rd() { return x(7, 5); }
  73   uint64_t rs1() { return x(15, 5); }
  74   uint64_t rs2() { return x(20, 5); }
  75   uint64_t rs3() { return x(27, 5); }
  76   uint64_t rm() { return x(12, 3); }
  77   uint64_t csr() { return x(20, 12); }
  78
  79   int64_t rvc_imm() { return x(2, 5) + (xs(12, 1) << 5); }
  80   int64_t rvc_addi4spn_imm() { return (x(6, 1) << 2) + (x(5, 1) << 3) + (x(11, 2) << 4) + (x(7, 4) << 6); }
  81   int64_t rvc_addi16sp_imm() { return (x(6, 1) << 4) + (x(5, 1) << 5) + (x(2, 3) << 6) + (xs(12, 1) << 9); }
  82   int64_t rvc_lwsp_imm() { return (x(4, 3) << 2) + (x(12, 1) << 5) + (x(2, 2) << 6); }
  83   int64_t rvc_ldsp_imm() { return (x(5, 2) << 3) + (x(12, 1) << 5) + (x(2, 3) << 6); }
  84   int64_t rvc_swsp_imm() { return (x(9, 4) << 2) + (x(7, 2) << 6); }
  85   int64_t rvc_sdsp_imm() { return (x(10, 3) << 3) + (x(7, 3) << 6); }
  86   int64_t rvc_lw_imm() { return (x(6, 1) << 2) + (x(10, 3) << 3) + (x(5, 1) << 6); }
  87   int64_t rvc_ld_imm() { return (x(10, 3) << 3) + (x(5, 2) << 6); }
  88   int64_t rvc_j_imm() { return (x(3, 4) << 1) + (x(2, 1) << 5) + (xs(7, 6) << 6); }
  89   int64_t rvc_b_imm() { return (x(3, 4) << 1) + (x(2, 1) << 5) + (xs(10, 3) << 6); }
  90   int64_t rvc_simm3() { return x(10, 3); }
  91   uint64_t rvc_rd() { return rd(); }
  92   uint64_t rvc_rs1() { return rd(); }
  93   uint64_t rvc_rs2() { return x(2, 5); }
  94   uint64_t rvc_rs1s() { return 8 + x(7, 3); }
  95   uint64_t rvc_rs2s() { return 8 + x(2, 3); }
  96 private:
  97   insn_bits_t b;
  98   uint64_t x(int lo, int len) { return (b >> lo) & ((insn_bits_t(1) << len)-1); }
  99   uint64_t xs(int lo, int len) { return int64_t(b) << (64-lo-len) >> (64-len); }
 100   uint64_t imm_sign() { return xs(63, 1); }
 101 };
 102
 103 template <class T, size_t N, bool zero_reg>
 104 class regfile_t
 105 {
 106 public:
 107   void write(size_t i, T value)
 108   {
 109     if (!zero_reg || i != 0)
 110       data[i] = value;
 111   }
 112   const T& operator [] (size_t i) const
 113   {
 114     return data[i];
 115   }
 116 private:
 117   T data[N];
 118 };
 119
 120 // helpful macros, etc
 121 #define MMU (*p->get_mmu())
 122 #define STATE (*p->get_state())
 123 #define READ_REG(reg) STATE.XPR[reg]
 124 #define RS1 READ_REG(insn.rs1())
 125 #define RS2 READ_REG(insn.rs2())
 126 #define WRITE_RD(value) WRITE_REG(insn.rd(), value)
 127
 128 #ifndef RISCV_ENABLE_COMMITLOG
 129 # define WRITE_REG(reg, value) STATE.XPR.write(reg, value)
 130 # define WRITE_FREG(reg, value) DO_WRITE_FREG(reg, value)
 131 #else
 132 # define WRITE_REG(reg, value) ({ \
 133     reg_t wdata = (value); /* value may have side effects */ \
 134     STATE.log_reg_write = (commit_log_reg_t){(reg) << 1, wdata}; \
 135     STATE.XPR.write(reg, wdata); \
 136   })
 137 # define WRITE_FREG(reg, value) ({ \
 138     freg_t wdata = (value); /* value may have side effects */ \
 139     STATE.log_reg_write = (commit_log_reg_t){((reg) << 1) | 1, wdata}; \
 140     DO_WRITE_FREG(reg, wdata); \
 141   })
 142 #endif
 143
 144 // RVC macros
 145 #define WRITE_RVC_RS2S(value) WRITE_REG(insn.rvc_rs2s(), value)
 146 #define WRITE_RVC_FRS2S(value) WRITE_FREG(insn.rvc_rs2s(), value)
 147 #define RVC_RS1 READ_REG(insn.rvc_rs1())
 148 #define RVC_RS2 READ_REG(insn.rvc_rs2())
 149 #define RVC_RS1S READ_REG(insn.rvc_rs1s())
 150 #define RVC_RS2S READ_REG(insn.rvc_rs2s())
 151 #define RVC_FRS2 STATE.FPR[insn.rvc_rs2()]
 152 #define RVC_FRS2S STATE.FPR[insn.rvc_rs2s()]
 153 #define RVC_SP READ_REG(X_SP)
 154
 155 // FPU macros
 156 #define FRS1 STATE.FPR[insn.rs1()]
 157 #define FRS2 STATE.FPR[insn.rs2()]
 158 #define FRS3 STATE.FPR[insn.rs3()]
 159 #define dirty_fp_state (STATE.mstatus |= MSTATUS_FS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))
 160 #define dirty_ext_state (STATE.mstatus |= MSTATUS_XS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))
 161 #define DO_WRITE_FREG(reg, value) (STATE.FPR.write(reg, value), dirty_fp_state)
 162 #define WRITE_FRD(value) WRITE_FREG(insn.rd(), value)
 163
 164 #define SHAMT (insn.i_imm() & 0x3F)
 165 #define BRANCH_TARGET (pc + insn.sb_imm())
 166 #define JUMP_TARGET (pc + insn.uj_imm())
 167 #define RM ({ int rm = insn.rm(); \
 168               if(rm == 7) rm = STATE.frm; \
 169               if(rm > 4) throw trap_illegal_instruction(); \
 170               rm; })
 171
 172 #define get_field(reg, mask) (((reg) & (decltype(reg))(mask)) / ((mask) & ~((mask) << 1)))
 173 #define set_field(reg, mask, val) (((reg) & ~(decltype(reg))(mask)) | (((decltype(reg))(val) * ((mask) & ~((mask) << 1))) & (decltype(reg))(mask)))
 174
 175 #define require(x) if (unlikely(!(x))) throw trap_illegal_instruction()
 176 #define require_privilege(p) require(get_field(STATE.mstatus, MSTATUS_PRV) >= (p))
 177 #define require_rv64 require(xlen == 64)
 178 #define require_rv32 require(xlen == 32)
 179 #define require_extension(s) require(p->supports_extension(s))
 180 #define require_fp require((STATE.mstatus & MSTATUS_FS) != 0)
 181 #define require_accelerator require((STATE.mstatus & MSTATUS_XS) != 0)
 182
 183 #define set_fp_exceptions ({ STATE.fflags |= softfloat_exceptionFlags; \
 184                              softfloat_exceptionFlags = 0; })
 185
 186 #define sext32(x) ((sreg_t)(int32_t)(x))
 187 #define zext32(x) ((reg_t)(uint32_t)(x))
 188 #define sext_xlen(x) (((sreg_t)(x) << (64-xlen)) >> (64-xlen))
 189 #define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen))
 190
 191 #define set_pc(x) \
 192   do { if (unlikely(((x) & 2)) && !p->supports_extension('C')) \
 193          throw trap_instruction_address_misaligned(x); \
 194        npc = sext_xlen(x); \
 195      } while(0)
 196
 197 #define PC_SERIALIZE 3 /* sentinel value indicating simulator pipeline flush */
 198
 199 #define validate_csr(which, write) ({ \
 200   if (!STATE.serialized) return PC_SERIALIZE; \
 201   STATE.serialized = false; \
 202   unsigned my_priv = get_field(STATE.mstatus, MSTATUS_PRV); \
 203   unsigned csr_priv = get_field((which), 0x300); \
 204   unsigned csr_read_only = get_field((which), 0xC00) == 3; \
 205   if (((write) && csr_read_only) || my_priv < csr_priv) \
 206     throw trap_illegal_instruction(); \
 207   (which); })
 208
 209 #endif