riscv/decode.h

   1 #ifndef _RISCV_DECODE_H
   2 #define _RISCV_DECODE_H
   3
   4 #define __STDC_LIMIT_MACROS
   5 #include <stdint.h>
   6 #include <string.h>
   7 #include "pcr.h"
   8 #include "config.h"
   9
  10 typedef int int128_t __attribute__((mode(TI)));
  11 typedef unsigned int uint128_t __attribute__((mode(TI)));
  12
  13 typedef int64_t sreg_t;
  14 typedef uint64_t reg_t;
  15 typedef uint64_t freg_t;
  16
  17 const int OPCODE_BITS = 7;
  18
  19 const int XPRID_BITS = 5;
  20 const int NXPR = 1 << XPRID_BITS;
  21
  22 const int FPR_BITS = 64;
  23 const int FPRID_BITS = 5;
  24 const int NFPR = 1 << FPRID_BITS;
  25
  26 const int IMM_BITS = 12;
  27 const int IMMLO_BITS = 7;
  28 const int TARGET_BITS = 25;
  29 const int FUNCT_BITS = 3;
  30 const int FUNCTR_BITS = 7;
  31 const int FFUNCT_BITS = 2;
  32 const int RM_BITS = 3;
  33 const int BIGIMM_BITS = 20;
  34 const int BRANCH_ALIGN_BITS = 1;
  35 const int JUMP_ALIGN_BITS = 1;
  36
  37 #define FP_RD_NE  0
  38 #define FP_RD_0   1
  39 #define FP_RD_DN  2
  40 #define FP_RD_UP  3
  41 #define FP_RD_NMM 4
  42
  43 #define FSR_RD_SHIFT 5
  44 #define FSR_RD   (0x7 << FSR_RD_SHIFT)
  45
  46 #define FPEXC_NX 0x01
  47 #define FPEXC_UF 0x02
  48 #define FPEXC_OF 0x04
  49 #define FPEXC_DZ 0x08
  50 #define FPEXC_NV 0x10
  51
  52 #define FSR_AEXC_SHIFT 0
  53 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
  54 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
  55 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
  56 #define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)
  57 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
  58 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  59
  60 #define FSR_ZERO ~(FSR_RD | FSR_AEXC)
  61
  62 // note: bit fields are in little-endian order
  63 struct itype_t
  64 {
  65   unsigned opcode : OPCODE_BITS;
  66   unsigned funct : FUNCT_BITS;
  67   signed imm12 : IMM_BITS;
  68   unsigned rs1 : XPRID_BITS;
  69   unsigned rd : XPRID_BITS;
  70 };
  71
  72 struct btype_t
  73 {
  74   unsigned opcode : OPCODE_BITS;
  75   unsigned funct : FUNCT_BITS;
  76   unsigned immlo : IMMLO_BITS;
  77   unsigned rs2 : XPRID_BITS;
  78   unsigned rs1 : XPRID_BITS;
  79   signed immhi : IMM_BITS-IMMLO_BITS;
  80 };
  81
  82 struct jtype_t
  83 {
  84   unsigned jump_opcode : OPCODE_BITS;
  85   signed target : TARGET_BITS;
  86 };
  87
  88 struct rtype_t
  89 {
  90   unsigned opcode : OPCODE_BITS;
  91   unsigned funct : FUNCT_BITS;
  92   unsigned functr : FUNCTR_BITS;
  93   unsigned rs2 : XPRID_BITS;
  94   unsigned rs1 : XPRID_BITS;
  95   unsigned rd : XPRID_BITS;
  96 };
  97
  98 struct ltype_t
  99 {
 100   unsigned opcode : OPCODE_BITS;
 101   unsigned bigimm : BIGIMM_BITS;
 102   unsigned rd : XPRID_BITS;
 103 };
 104
 105 struct ftype_t
 106 {
 107   unsigned opcode : OPCODE_BITS;
 108   unsigned ffunct : FFUNCT_BITS;
 109   unsigned rm : RM_BITS;
 110   unsigned rs3 : FPRID_BITS;
 111   unsigned rs2 : FPRID_BITS;
 112   unsigned rs1 : FPRID_BITS;
 113   unsigned rd  : FPRID_BITS;
 114 };
 115
 116 union insn_t
 117 {
 118   itype_t itype;
 119   jtype_t jtype;
 120   rtype_t rtype;
 121   btype_t btype;
 122   ltype_t ltype;
 123   ftype_t ftype;
 124   uint32_t bits;
 125 };
 126
 127 template <class T>
 128 class write_port_t
 129 {
 130 public:
 131   write_port_t(T& _t) : t(_t) {}
 132   T& operator = (const T& rhs)
 133   {
 134     return t = rhs;
 135   }
 136   operator T()
 137   {
 138     return t;
 139   }
 140 private:
 141   T& t;
 142 };
 143 template <class T, size_t N, bool zero_reg>
 144 class regfile_t
 145 {
 146 public:
 147   void reset()
 148   {
 149     memset(data, 0, sizeof(data));
 150   }
 151   write_port_t<T> write_port(size_t i)
 152   {
 153     return write_port_t<T>(data[i]);
 154   }
 155   const T& operator [] (size_t i) const
 156   {
 157     if (zero_reg)
 158       const_cast<T&>(data[0]) = 0;
 159     return data[i];
 160   }
 161 private:
 162   T data[N];
 163 };
 164
 165 #define throw_illegal_instruction \
 166   ({ if (utmode) throw trap_vector_illegal_instruction; \
 167      else throw trap_illegal_instruction; })
 168
 169 // helpful macros, etc
 170 #define RS1 XPR[insn.rtype.rs1]
 171 #define RS2 XPR[insn.rtype.rs2]
 172 #define RD XPR.write_port(insn.rtype.rd)
 173 #define RA XPR.write_port(1)
 174 #define FRS1 FPR[insn.ftype.rs1]
 175 #define FRS2 FPR[insn.ftype.rs2]
 176 #define FRS3 FPR[insn.ftype.rs3]
 177 #define FRD FPR.write_port(insn.ftype.rd)
 178 #define BIGIMM insn.ltype.bigimm
 179 #define SIMM insn.itype.imm12
 180 #define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS))
 181 #define SHAMT (insn.itype.imm12 & 0x3F)
 182 #define SHAMTW (insn.itype.imm12 & 0x1F)
 183 #define TARGET insn.jtype.target
 184 #define BRANCH_TARGET (pc + (BIMM << BRANCH_ALIGN_BITS))
 185 #define JUMP_TARGET (pc + (TARGET << JUMP_ALIGN_BITS))
 186 #define ITYPE_EADDR sext_xprlen(RS1 + SIMM)
 187 #define BTYPE_EADDR sext_xprlen(RS1 + BIMM)
 188 #define RM ({ int rm = insn.ftype.rm; \
 189               if(rm == 7) rm = (fsr & FSR_RD) >> FSR_RD_SHIFT; \
 190               if(rm > 4) throw_illegal_instruction; \
 191               rm; })
 192
 193 #define xpr64 (xprlen == 64)
 194
 195 #define require_supervisor if(unlikely(!(sr & SR_S))) throw trap_privileged_instruction
 196 #define require_xpr64 if(unlikely(!xpr64)) throw_illegal_instruction
 197 #define require_xpr32 if(unlikely(xpr64)) throw_illegal_instruction
 198 #ifndef RISCV_ENABLE_FPU
 199 # define require_fp throw trap_illegal_instruction
 200 #else
 201 # define require_fp if(unlikely(!(sr & SR_EF))) throw trap_fp_disabled
 202 #endif
 203 #ifndef RISCV_ENABLE_VEC
 204 # define require_vector throw trap_illegal_instruction
 205 #else
 206 # define require_vector \
 207   ({ if(!(sr & SR_EV)) throw trap_vector_disabled; \
 208     else if (!utmode && (vecbanks_count < 3)) throw trap_vector_bank; \
 209   })
 210 #endif
 211
 212 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
 213 #define set_fp_exceptions ({ set_fsr(fsr | \
 214                                (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
 215                              softfloat_exceptionFlags = 0; })
 216
 217 #define sext32(x) ((sreg_t)(int32_t)(x))
 218 #define zext32(x) ((reg_t)(uint32_t)(x))
 219 #define sext_xprlen(x) (((sreg_t)(x) << (64-xprlen)) >> (64-xprlen))
 220 #define zext_xprlen(x) (((reg_t)(x) << (64-xprlen)) >> (64-xprlen))
 221
 222 // RVC stuff
 223
 224 #define INSN_IS_RVC(x) (((x) & 0x3) < 0x3)
 225 #define insn_length(x) (INSN_IS_RVC(x) ? 2 : 4)
 226 #define require_rvc if(!(sr & SR_EC)) throw_illegal_instruction
 227
 228 #define CRD_REGNUM ((insn.bits >> 5) & 0x1f)
 229 #define CRD XPR.write_port(CRD_REGNUM)
 230 #define CRS1 XPR[(insn.bits >> 10) & 0x1f]
 231 #define CRS2 XPR[(insn.bits >> 5) & 0x1f]
 232 #define CIMM6 ((int32_t)((insn.bits >> 10) & 0x3f) << 26 >> 26)
 233 #define CIMM5U ((insn.bits >> 5) & 0x1f)
 234 #define CIMM5 ((int32_t)CIMM5U << 27 >> 27)
 235 #define CIMM10 ((int32_t)((insn.bits >> 5) & 0x3ff) << 22 >> 22)
 236 #define CBRANCH_TARGET (pc + (CIMM5 << BRANCH_ALIGN_BITS))
 237 #define CJUMP_TARGET (pc + (CIMM10 << JUMP_ALIGN_BITS))
 238
 239 static const int rvc_rs1_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 };
 240 #define rvc_rd_regmap rvc_rs1_regmap
 241 #define rvc_rs2b_regmap rvc_rs1_regmap
 242 static const int rvc_rs2_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 0 };
 243 #define CRDS XPR.write_port(rvc_rd_regmap[(insn.bits >> 13) & 0x7])
 244 #define FCRDS FPR.write_port(rvc_rd_regmap[(insn.bits >> 13) & 0x7])
 245 #define CRS1S XPR[rvc_rs1_regmap[(insn.bits >> 10) & 0x7]]
 246 #define CRS2S XPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
 247 #define CRS2BS XPR[rvc_rs2b_regmap[(insn.bits >> 5) & 0x7]]
 248 #define FCRS2S FPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
 249
 250 // vector stuff
 251 #define VL vl
 252
 253 #define UT_RS1(idx) uts[idx]->XPR[insn.rtype.rs1]
 254 #define UT_RS2(idx) uts[idx]->XPR[insn.rtype.rs2]
 255 #define UT_RD(idx) uts[idx]->XPR.write_port(insn.rtype.rd)
 256 #define UT_RA(idx) uts[idx]->XPR.write_port(1)
 257 #define UT_FRS1(idx) uts[idx]->FPR[insn.ftype.rs1]
 258 #define UT_FRS2(idx) uts[idx]->FPR[insn.ftype.rs2]
 259 #define UT_FRS3(idx) uts[idx]->FPR[insn.ftype.rs3]
 260 #define UT_FRD(idx) uts[idx]->FPR.write_port(insn.ftype.rd)
 261 #define UT_RM(idx) ((insn.ftype.rm != 7) ? insn.ftype.rm : \
 262               ((uts[idx]->fsr & FSR_RD) >> FSR_RD_SHIFT))
 263
 264 #define UT_LOOP_START for (int i=0;i<VL; i++) {
 265 #define UT_LOOP_END }
 266 #define UT_LOOP_RS1 UT_RS1(i)
 267 #define UT_LOOP_RS2 UT_RS2(i)
 268 #define UT_LOOP_RD UT_RD(i)
 269 #define UT_LOOP_RA UT_RA(i)
 270 #define UT_LOOP_FRS1 UT_FRS1(i)
 271 #define UT_LOOP_FRS2 UT_FRS2(i)
 272 #define UT_LOOP_FRS3 UT_FRS3(i)
 273 #define UT_LOOP_FRD UT_FRD(i)
 274 #define UT_LOOP_RM UT_RM(i)
 275
 276 #define VEC_LOAD(dst, func, inc) \
 277   reg_t addr = RS1; \
 278   UT_LOOP_START \
 279     UT_LOOP_##dst = mmu.func(addr); \
 280     addr += inc; \
 281   UT_LOOP_END
 282
 283 #define VEC_STORE(src, func, inc) \
 284   reg_t addr = RS1; \
 285   UT_LOOP_START \
 286     mmu.func(addr, UT_LOOP_##src); \
 287     addr += inc; \
 288   UT_LOOP_END
 289
 290 enum vt_command_t
 291 {
 292   vt_command_stop,
 293 };
 294
 295 #endif