riscv/decode.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_DECODE_H
   4 #define _RISCV_DECODE_H
   5
   6 #if (-1 != ~0) || ((-1 >> 1) != -1)
   7 # error spike requires a two''s-complement c++ implementation
   8 #endif
   9
  10 #include <cstdint>
  11 #include <string.h>
  12 #include <strings.h>
  13 #include "encoding.h"
  14 #include "config.h"
  15 #include "common.h"
  16 #include <cinttypes>
  17
  18 typedef int64_t sreg_t;
  19 typedef uint64_t reg_t;
  20 typedef uint64_t freg_t;
  21
  22 const int NXPR = 32;
  23 const int NFPR = 32;
  24 const int NCSR = 4096;
  25
  26 #define X_RA 1
  27 #define X_SP 2
  28
  29 #define FP_RD_NE  0
  30 #define FP_RD_0   1
  31 #define FP_RD_DN  2
  32 #define FP_RD_UP  3
  33 #define FP_RD_NMM 4
  34
  35 #define FSR_RD_SHIFT 5
  36 #define FSR_RD   (0x7 << FSR_RD_SHIFT)
  37
  38 #define FPEXC_NX 0x01
  39 #define FPEXC_UF 0x02
  40 #define FPEXC_OF 0x04
  41 #define FPEXC_DZ 0x08
  42 #define FPEXC_NV 0x10
  43
  44 #define FSR_AEXC_SHIFT 0
  45 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
  46 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
  47 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
  48 #define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)
  49 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
  50 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  51
  52 #define insn_length(x) \
  53   (((x) & 0x03) < 0x03 ? 2 : \
  54    ((x) & 0x1f) < 0x1f ? 4 : \
  55    ((x) & 0x3f) < 0x3f ? 6 : \
  56    8)
  57 #define MAX_INSN_LENGTH 8
  58 #define PC_ALIGN 2
  59
  60 typedef uint64_t insn_bits_t;
  61 class insn_t
  62 {
  63 public:
  64   insn_t() = default;
  65   insn_t(insn_bits_t bits) : b(bits) {}
  66   insn_bits_t bits() { return b; }
  67   int length() { return insn_length(b); }
  68   int64_t i_imm() { return int64_t(b) >> 20; }
  69   int64_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); }
  70   int64_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); }
  71   int64_t u_imm() { return int64_t(b) >> 12 << 12; }
  72   int64_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); }
  73   uint64_t rd() { return x(7, 5); }
  74   uint64_t rs1() { return x(15, 5); }
  75   uint64_t rs2() { return x(20, 5); }
  76   uint64_t rs3() { return x(27, 5); }
  77   uint64_t rm() { return x(12, 3); }
  78   uint64_t csr() { return x(20, 12); }
  79
  80   int64_t rvc_imm() { return x(2, 5) + (xs(12, 1) << 5); }
  81   int64_t rvc_zimm() { return x(2, 5) + (x(12, 1) << 5); }
  82   int64_t rvc_addi4spn_imm() { return (x(6, 1) << 2) + (x(5, 1) << 3) + (x(11, 2) << 4) + (x(7, 4) << 6); }
  83   int64_t rvc_addi16sp_imm() { return (x(6, 1) << 4) + (x(2, 1) << 5) + (x(5, 1) << 6) + (x(3, 2) << 7) + (xs(12, 1) << 9); }
  84   int64_t rvc_lwsp_imm() { return (x(4, 3) << 2) + (x(12, 1) << 5) + (x(2, 2) << 6); }
  85   int64_t rvc_ldsp_imm() { return (x(5, 2) << 3) + (x(12, 1) << 5) + (x(2, 3) << 6); }
  86   int64_t rvc_swsp_imm() { return (x(9, 4) << 2) + (x(7, 2) << 6); }
  87   int64_t rvc_sdsp_imm() { return (x(10, 3) << 3) + (x(7, 3) << 6); }
  88   int64_t rvc_lw_imm() { return (x(6, 1) << 2) + (x(10, 3) << 3) + (x(5, 1) << 6); }
  89   int64_t rvc_ld_imm() { return (x(10, 3) << 3) + (x(5, 2) << 6); }
  90   int64_t rvc_j_imm() { return (x(3, 3) << 1) + (x(11, 1) << 4) + (x(2, 1) << 5) + (x(7, 1) << 6) + (x(6, 1) << 7) + (x(9, 2) << 8) + (x(8, 1) << 10) + (xs(12, 1) << 11); }
  91   int64_t rvc_b_imm() { return (x(3, 2) << 1) + (x(10, 2) << 3) + (x(2, 1) << 5) + (x(5, 2) << 6) + (xs(12, 1) << 8); }
  92   int64_t rvc_simm3() { return x(10, 3); }
  93   uint64_t rvc_rd() { return rd(); }
  94   uint64_t rvc_rs1() { return rd(); }
  95   uint64_t rvc_rs2() { return x(2, 5); }
  96   uint64_t rvc_rs1s() { return 8 + x(7, 3); }
  97   uint64_t rvc_rs2s() { return 8 + x(2, 3); }
  98 private:
  99   insn_bits_t b;
 100   uint64_t x(int lo, int len) { return (b >> lo) & ((insn_bits_t(1) << len)-1); }
 101   uint64_t xs(int lo, int len) { return int64_t(b) << (64-lo-len) >> (64-len); }
 102   uint64_t imm_sign() { return xs(63, 1); }
 103 };
 104
 105 template <class T, size_t N, bool zero_reg>
 106 class regfile_t
 107 {
 108 public:
 109   void write(size_t i, T value)
 110   {
 111     if (!zero_reg || i != 0)
 112       data[i] = value;
 113   }
 114   const T& operator [] (size_t i) const
 115   {
 116     return data[i];
 117   }
 118 private:
 119   T data[N];
 120 };
 121
 122 // helpful macros, etc
 123 #define MMU (*p->get_mmu())
 124 #define STATE (*p->get_state())
 125 #define READ_REG(reg) STATE.XPR[reg]
 126 #define READ_FREG(reg) STATE.FPR[reg]
 127 #define RS1 READ_REG(insn.rs1())
 128 #define RS2 READ_REG(insn.rs2())
 129 #define WRITE_RD(value) WRITE_REG(insn.rd(), value)
 130
 131 #ifndef RISCV_ENABLE_COMMITLOG
 132 # define WRITE_REG(reg, value) STATE.XPR.write(reg, value)
 133 # define WRITE_FREG(reg, value) DO_WRITE_FREG(reg, value)
 134 #else
 135 # define WRITE_REG(reg, value) ({ \
 136     reg_t wdata = (value); /* value may have side effects */ \
 137     STATE.log_reg_write = (commit_log_reg_t){(reg) << 1, wdata}; \
 138     STATE.XPR.write(reg, wdata); \
 139   })
 140 # define WRITE_FREG(reg, value) ({ \
 141     freg_t wdata = (value); /* value may have side effects */ \
 142     STATE.log_reg_write = (commit_log_reg_t){((reg) << 1) | 1, wdata}; \
 143     DO_WRITE_FREG(reg, wdata); \
 144   })
 145 #endif
 146
 147 // RVC macros
 148 #define WRITE_RVC_RS1S(value) WRITE_REG(insn.rvc_rs1s(), value)
 149 #define WRITE_RVC_RS2S(value) WRITE_REG(insn.rvc_rs2s(), value)
 150 #define WRITE_RVC_FRS2S(value) WRITE_FREG(insn.rvc_rs2s(), value)
 151 #define RVC_RS1 READ_REG(insn.rvc_rs1())
 152 #define RVC_RS2 READ_REG(insn.rvc_rs2())
 153 #define RVC_RS1S READ_REG(insn.rvc_rs1s())
 154 #define RVC_RS2S READ_REG(insn.rvc_rs2s())
 155 #define RVC_FRS2 READ_FREG(insn.rvc_rs2())
 156 #define RVC_FRS2S READ_FREG(insn.rvc_rs2s())
 157 #define RVC_SP READ_REG(X_SP)
 158
 159 // FPU macros
 160 #define FRS1 READ_FREG(insn.rs1())
 161 #define FRS2 READ_FREG(insn.rs2())
 162 #define FRS3 READ_FREG(insn.rs3())
 163 #define dirty_fp_state (STATE.mstatus |= MSTATUS_FS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))
 164 #define dirty_ext_state (STATE.mstatus |= MSTATUS_XS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))
 165 #define DO_WRITE_FREG(reg, value) (STATE.FPR.write(reg, value), dirty_fp_state)
 166 #define WRITE_FRD(value) WRITE_FREG(insn.rd(), value)
 167
 168 #define SHAMT (insn.i_imm() & 0x3F)
 169 #define BRANCH_TARGET (pc + insn.sb_imm())
 170 #define JUMP_TARGET (pc + insn.uj_imm())
 171 #define RM ({ int rm = insn.rm(); \
 172               if(rm == 7) rm = STATE.frm; \
 173               if(rm > 4) throw trap_illegal_instruction(); \
 174               rm; })
 175
 176 #define get_field(reg, mask) (((reg) & (decltype(reg))(mask)) / ((mask) & ~((mask) << 1)))
 177 #define set_field(reg, mask, val) (((reg) & ~(decltype(reg))(mask)) | (((decltype(reg))(val) * ((mask) & ~((mask) << 1))) & (decltype(reg))(mask)))
 178
 179 #define require(x) if (unlikely(!(x))) throw trap_illegal_instruction()
 180 #define require_privilege(p) require(STATE.prv >= (p))
 181 #define require_rv64 require(xlen == 64)
 182 #define require_rv32 require(xlen == 32)
 183 #define require_extension(s) require(p->supports_extension(s))
 184 #define require_fp require((STATE.mstatus & MSTATUS_FS) != 0)
 185 #define require_accelerator require((STATE.mstatus & MSTATUS_XS) != 0)
 186
 187 #define set_fp_exceptions ({ if (softfloat_exceptionFlags) { \
 188                                dirty_fp_state; \
 189                                STATE.fflags |= softfloat_exceptionFlags; \
 190                              } \
 191                              softfloat_exceptionFlags = 0; })
 192
 193 #define sext32(x) ((sreg_t)(int32_t)(x))
 194 #define zext32(x) ((reg_t)(uint32_t)(x))
 195 #define sext_xlen(x) (((sreg_t)(x) << (64-xlen)) >> (64-xlen))
 196 #define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen))
 197
 198 #define set_pc(x) \
 199   do { if (unlikely(((x) & 2)) && !p->supports_extension('C')) \
 200          throw trap_instruction_address_misaligned(x); \
 201        npc = sext_xlen(x); \
 202      } while(0)
 203
 204 #define set_pc_and_serialize(x) \
 205   do { reg_t __npc = (x); \
 206        set_pc(__npc); /* check alignment */ \
 207        npc = PC_SERIALIZE_AFTER; \
 208        STATE.pc = __npc; \
 209      } while(0)
 210
 211 /* Sentinel PC values to serialize simulator pipeline */
 212 #define PC_SERIALIZE_BEFORE 3
 213 #define PC_SERIALIZE_AFTER 5
 214 #define invalid_pc(pc) ((pc) & 1)
 215
 216 /* Convenience wrappers to simplify softfloat code sequences */
 217 #define f32(x) ((float32_t){(uint32_t)x})
 218 #define f64(x) ((float64_t){(uint64_t)x})
 219
 220 #define validate_csr(which, write) ({ \
 221   if (!STATE.serialized) return PC_SERIALIZE_BEFORE; \
 222   STATE.serialized = false; \
 223   unsigned csr_priv = get_field((which), 0x300); \
 224   unsigned csr_read_only = get_field((which), 0xC00) == 3; \
 225   if (((write) && csr_read_only) || STATE.prv < csr_priv) \
 226     throw trap_illegal_instruction(); \
 227   (which); })
 228
 229 #define DEBUG_START             0x100
 230 #define DEBUG_ROM_START         0x800
 231 #define DEBUG_ROM_RESUME        (DEBUG_ROM_START + 4)
 232 #define DEBUG_ROM_EXCEPTION     (DEBUG_ROM_START + 8)
 233 #define DEBUG_ROM_END           (DEBUG_ROM_START + debug_rom_raw_len)
 234 #define DEBUG_RAM_START         0x400
 235 #define DEBUG_RAM_SIZE          64
 236 #define DEBUG_RAM_END           (DEBUG_RAM_START + DEBUG_RAM_SIZE)
 237 #define DEBUG_END               0xfff
 238 #define DEBUG_CLEARDEBINT       0x100
 239 #define DEBUG_SETHALTNOT        0x10c
 240 #define DEBUG_SIZE              (DEBUG_END - DEBUG_START + 1)
 241
 242 #endif