riscv/execute.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "mmu.h"
   5 #include "sim.h"
   6 #include <cassert>
   7
   8
   9 static void commit_log_stash_privilege(processor_t* p)
  10 {
  11 #ifdef RISCV_ENABLE_COMMITLOG
  12   state_t* state = p->get_state();
  13   state->last_inst_priv = state->prv;
  14   state->last_inst_xlen = p->get_xlen();
  15   state->last_inst_flen = p->get_flen();
  16 #endif
  17 }
  18
  19 static void commit_log_print_value(int width, uint64_t hi, uint64_t lo)
  20 {
  21   switch (width) {
  22     case 16:
  23       fprintf(stderr, "0x%04" PRIx16, (uint16_t)lo);
  24       break;
  25     case 32:
  26       fprintf(stderr, "0x%08" PRIx32, (uint32_t)lo);
  27       break;
  28     case 64:
  29       fprintf(stderr, "0x%016" PRIx64, lo);
  30       break;
  31     case 128:
  32       fprintf(stderr, "0x%016" PRIx64 "%016" PRIx64, hi, lo);
  33       break;
  34     default:
  35       abort();
  36   }
  37 }
  38
  39 static void commit_log_print_insn(state_t* state, reg_t pc, insn_t insn)
  40 {
  41 #ifdef RISCV_ENABLE_COMMITLOG
  42   auto& reg = state->log_reg_write;
  43   int priv = state->last_inst_priv;
  44   int xlen = state->last_inst_xlen;
  45   int flen = state->last_inst_flen;
  46
  47   fprintf(stderr, "%1d ", priv);
  48   commit_log_print_value(xlen, 0, pc);
  49   fprintf(stderr, " (");
  50   commit_log_print_value(insn.length() * 8, 0, insn.bits());
  51
  52   if (reg.addr) {
  53     bool fp = reg.addr & 1;
  54     int rd = reg.addr >> 1;
  55     int size = fp ? flen : xlen;
  56     fprintf(stderr, ") %c%2d ", fp ? 'f' : 'x', rd);
  57     commit_log_print_value(size, reg.data.v[1], reg.data.v[0]);
  58     fprintf(stderr, "\n");
  59   } else {
  60     fprintf(stderr, ")\n");
  61   }
  62   reg.addr = 0;
  63 #endif
  64 }
  65
  66 inline void processor_t::update_histogram(reg_t pc)
  67 {
  68 #ifdef RISCV_ENABLE_HISTOGRAM
  69   pc_histogram[pc]++;
  70 #endif
  71 }
  72
  73 // This is expected to be inlined by the compiler so each use of execute_insn
  74 // includes a duplicated body of the function to get separate fetch.func
  75 // function calls.
  76 static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
  77 {
  78   commit_log_stash_privilege(p);
  79   reg_t npc = fetch.func(p, fetch.insn, pc);
  80   if (!invalid_pc(npc)) {
  81     commit_log_print_insn(p->get_state(), pc, fetch.insn);
  82     p->update_histogram(pc);
  83   }
  84   return npc;
  85 }
  86
  87 bool processor_t::slow_path()
  88 {
  89   return debug || state.single_step != state.STEP_NONE || state.dcsr.cause;
  90 }
  91
  92 // fetch/decode/execute loop
  93 void processor_t::step(size_t n)
  94 {
  95   if (state.dcsr.cause == DCSR_CAUSE_NONE) {
  96     if (halt_request) {
  97       enter_debug_mode(DCSR_CAUSE_DEBUGINT);
  98     } // !!!The halt bit in DCSR is deprecated.
  99     else if (state.dcsr.halt) {
 100       enter_debug_mode(DCSR_CAUSE_HALT);
 101     }
 102   }
 103
 104   while (n > 0) {
 105     size_t instret = 0;
 106     reg_t pc = state.pc;
 107     mmu_t* _mmu = mmu;
 108
 109     #define advance_pc() \
 110      if (unlikely(invalid_pc(pc))) { \
 111        switch (pc) { \
 112          case PC_SERIALIZE_BEFORE: state.serialized = true; break; \
 113          case PC_SERIALIZE_AFTER: n = ++instret; break; \
 114          default: abort(); \
 115        } \
 116        pc = state.pc; \
 117        break; \
 118      } else { \
 119        state.pc = pc; \
 120        instret++; \
 121      }
 122
 123     try
 124     {
 125       take_pending_interrupt();
 126
 127       if (unlikely(slow_path()))
 128       {
 129         while (instret < n)
 130         {
 131           if (unlikely(state.single_step == state.STEP_STEPPING)) {
 132             state.single_step = state.STEP_STEPPED;
 133           }
 134
 135           insn_fetch_t fetch = mmu->load_insn(pc);
 136           if (debug && !state.serialized)
 137             disasm(fetch.insn);
 138           pc = execute_insn(this, pc, fetch);
 139           bool serialize_before = (pc == PC_SERIALIZE_BEFORE);
 140
 141           advance_pc();
 142
 143           if (unlikely(state.single_step == state.STEP_STEPPED) && !serialize_before) {
 144             state.single_step = state.STEP_NONE;
 145             enter_debug_mode(DCSR_CAUSE_STEP);
 146             // enter_debug_mode changed state.pc, so we can't just continue.
 147             break;
 148           }
 149
 150           if (unlikely(state.pc >= DEBUG_ROM_ENTRY &&
 151                        state.pc < DEBUG_END)) {
 152             // We're waiting for the debugger to tell us something.
 153             return;
 154           }
 155
 156         }
 157       }
 158       else while (instret < n)
 159       {
 160         // This code uses a modified Duff's Device to improve the performance
 161         // of executing instructions. While typical Duff's Devices are used
 162         // for software pipelining, the switch statement below primarily
 163         // benefits from separate call points for the fetch.func function call
 164         // found in each execute_insn. This function call is an indirect jump
 165         // that depends on the current instruction. By having an indirect jump
 166         // dedicated for each icache entry, you improve the performance of the
 167         // host's next address predictor. Each case in the switch statement
 168         // allows for the program flow to contine to the next case if it
 169         // corresponds to the next instruction in the program and instret is
 170         // still less than n.
 171         //
 172         // According to Andrew Waterman's recollection, this optimization
 173         // resulted in approximately a 2x performance increase.
 174
 175         // This figures out where to jump to in the switch statement
 176         size_t idx = _mmu->icache_index(pc);
 177
 178         // This gets the cached decoded instruction from the MMU. If the MMU
 179         // does not have the current pc cached, it will refill the MMU and
 180         // return the correct entry. ic_entry->data.func is the C++ function
 181         // corresponding to the instruction.
 182         auto ic_entry = _mmu->access_icache(pc);
 183
 184         // This macro is included in "icache.h" included within the switch
 185         // statement below. The indirect jump corresponding to the instruction
 186         // is located within the execute_insn() function call.
 187         #define ICACHE_ACCESS(i) { \
 188           insn_fetch_t fetch = ic_entry->data; \
 189           pc = execute_insn(this, pc, fetch); \
 190           ic_entry = ic_entry->next; \
 191           if (i == mmu_t::ICACHE_ENTRIES-1) break; \
 192           if (unlikely(ic_entry->tag != pc)) break; \
 193           if (unlikely(instret+1 == n)) break; \
 194           instret++; \
 195           state.pc = pc; \
 196         }
 197
 198         // This switch statement implements the modified Duff's device as
 199         // explained above.
 200         switch (idx) {
 201           // "icache.h" is generated by the gen_icache script
 202           #include "icache.h"
 203         }
 204
 205         advance_pc();
 206       }
 207     }
 208     catch(trap_t& t)
 209     {
 210       take_trap(t, pc);
 211       n = instret;
 212
 213       if (unlikely(state.single_step == state.STEP_STEPPED)) {
 214         state.single_step = state.STEP_NONE;
 215         enter_debug_mode(DCSR_CAUSE_STEP);
 216       }
 217     }
 218     catch (trigger_matched_t& t)
 219     {
 220       if (mmu->matched_trigger) {
 221         // This exception came from the MMU. That means the instruction hasn't
 222         // fully executed yet. We start it again, but this time it won't throw
 223         // an exception because matched_trigger is already set. (All memory
 224         // instructions are idempotent so restarting is safe.)
 225
 226         insn_fetch_t fetch = mmu->load_insn(pc);
 227         pc = execute_insn(this, pc, fetch);
 228         advance_pc();
 229
 230         delete mmu->matched_trigger;
 231         mmu->matched_trigger = NULL;
 232       }
 233       switch (state.mcontrol[t.index].action) {
 234         case ACTION_DEBUG_MODE:
 235           enter_debug_mode(DCSR_CAUSE_HWBP);
 236           break;
 237         case ACTION_DEBUG_EXCEPTION: {
 238           mem_trap_t trap(CAUSE_BREAKPOINT, t.address);
 239           take_trap(trap, pc);
 240           break;
 241         }
 242         default:
 243           abort();
 244       }
 245     }
 246
 247     state.minstret += instret;
 248     n -= instret;
 249   }
 250 }