034743a833847351996948ffa6e517db9ae25bb3
[riscv-isa-sim.git] / riscv / htif.h
1 #ifndef _HTIF_H
2 #define _HTIF_H
3
4 #include <fesvr/htif_pthread.h>
5
6 class sim_t;
7 struct packet;
8
9 // this class implements the host-target interface for program loading, etc.
10 // a simpler implementation would implement the high-level interface
11 // (read/write cr, read/write chunk) directly, but we implement the lower-
12 // level serialized interface to be more similar to real target machines.
13
14 class htif_isasim_t : public htif_pthread_t
15 {
16 public:
17 htif_isasim_t(sim_t* _sim, const std::vector<std::string>& args);
18 void tick();
19 bool done();
20
21 private:
22 sim_t* sim;
23 bool reset;
24 uint8_t seqno;
25
26 void tick_once();
27 };
28
29 #endif