4e1025e7b5e94e4986475fc9c7c79cd1113fad41
[riscv-isa-sim.git] / riscv / htif.h
1 // See LICENSE for license details.
2
3 #ifndef _HTIF_H
4 #define _HTIF_H
5
6 #include <fesvr/htif_pthread.h>
7
8 class sim_t;
9 struct packet;
10
11 // this class implements the host-target interface for program loading, etc.
12 // a simpler implementation would implement the high-level interface
13 // (read/write cr, read/write chunk) directly, but we implement the lower-
14 // level serialized interface to be more similar to real target machines.
15
16 class htif_isasim_t : public htif_pthread_t
17 {
18 public:
19 htif_isasim_t(sim_t* _sim, const std::vector<std::string>& args);
20 bool tick();
21 bool done();
22
23 private:
24 sim_t* sim;
25 bool reset;
26 uint8_t seqno;
27
28 void tick_once();
29 };
30
31 #endif