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32ea7f70fa9a643c598e663898b655c8269011cd
[riscv-isa-sim.git]
/
riscv
/
insns
/
amoand_w.h
1
reg_t v
=
MMU
.
load_int32
(
RS1
);
2
MMU
.
store_uint32
(
RS1
,
RS2
&
v
);
3
WRITE_RD
(
v
);