448e31a337ce97b709710b5d979ee52c436b95de
[riscv-isa-sim.git] / riscv / insns / c_addi.h
1 require_rvc;
2 if(CRD_REGNUM == 0)
3 {
4 reg_t temp = CRS1;
5 if(CIMM6 & 0x20)
6 RA = npc;
7 set_pc(temp);
8 }
9 else
10 CRD = sext_xprlen(CRS2 + CIMM6);