ae4980edce24b3bf7650c2ba34a8bd1aedb46c42
[riscv-isa-sim.git] / riscv / insns / c_addiw.h
1 require_extension('C');
2 if (xlen == 32) {
3 WRITE_RD(RVC_RS1 & insn.rvc_imm()); // c.andi
4 } else {
5 require(insn.rvc_rd() != 0);
6 WRITE_RD(sext32(RVC_RS1 + insn.rvc_imm()));
7 }