8923fef38fb1a5f88780cb1d893736809126b16a
[riscv-isa-sim.git] / riscv / insns / c_fsw.h
1 require_extension('C');
2 if (xlen == 32) {
3 require_extension('F');
4 require_fp;
5 MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S);
6 } else { // c.sd
7 MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S);
8 }