c13aa12f8908c1819402319dc5c09e416420d7cf
[riscv-isa-sim.git] / riscv / insns / c_fswsp.h
1 require_extension('C');
2 if (xlen == 32) {
3 require_extension('F');
4 require_fp;
5 MMU.store_uint32(RVC_SP + insn.rvc_swsp_imm(), RVC_FRS2);
6 } else { // c.sdsp
7 MMU.store_uint64(RVC_SP + insn.rvc_sdsp_imm(), RVC_RS2);
8 }