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aa98f3365daa3005c3ad6c318dce0b90ba38f536
[riscv-isa-sim.git]
/
riscv
/
insns
/
c_ldsp.h
1
require_extension
(
'C'
);
2
if
(
xlen
==
32
) {
3
if
(
sreg_t
(
RVC_RS1S
) >=
0
)
// c.bgez
4
set_pc
(
pc
+
insn
.
rvc_b_imm
());
5
}
else
{
6
require
(
insn
.
rvc_rd
() !=
0
);
7
WRITE_RD
(
MMU
.
load_int64
(
RVC_SP
+
insn
.
rvc_ldsp_imm
()));
8
}