52e99c96005b996b87bce4b9552cb936bca69c6a
[riscv-isa-sim.git] / riscv / insns / c_li.h
1 require_extension('C');
2 require(insn.rvc_rd() != 0);
3 if (insn.rvc_imm() == 0) { // c.jr
4 set_pc(RVC_RS1 & ~reg_t(1));
5 } else {
6 WRITE_RD(insn.rvc_imm());
7 }