b53c958676997782e9eb90b86f9e22534b90640a
[riscv-isa-sim.git] / riscv / insns / c_li.h
1 require_rvc;
2 if (insn.rvc_rd() == 0) {
3 if (insn.rvc_imm() == -32) // c.sbreak
4 throw trap_breakpoint();
5 throw trap_illegal_instruction();
6 } else // c.li
7 WRITE_RD(insn.rvc_imm());