bd4e999f65dad1aa72dd91aa96b99e310991aed1
[riscv-isa-sim.git] / riscv / insns / divw.h
1 require_rv64;
2 sreg_t lhs = sext32(RS1);
3 sreg_t rhs = sext32(RS2);
4 if(rhs == 0)
5 WRITE_RD(UINT64_MAX);
6 else
7 WRITE_RD(sext32(lhs / rhs));