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5b4c4444bab2d0cceb8eebdbde5e1f8eb9124ec1
[riscv-isa-sim.git]
/
riscv
/
insns
/
fcvt_wu_s.h
1
require_fp
;
2
softfloat_roundingMode
=
RM
;
3
WRITE_RD
(
sext32
(
f32_to_ui32
(
FRS1
,
RM
,
true
)));
4
set_fp_exceptions
;