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b44da24e02b794536ff9535652427d7e97beb49b
[riscv-isa-sim.git]
/
riscv
/
insns
/
feq_s.h
1
require_fp
;
2
WRITE_RD
(
f32_eq
(
FRS1
,
FRS2
));
3
set_fp_exceptions
;