98f1cbc25cc5b2a99b438bb8b4d1362415b72a47
[riscv-isa-sim.git] / riscv / insns / fmadd_d.h
1 require_extension('D');
2 require_fp;
3 softfloat_roundingMode = RM;
4 WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(FRS3)).v);
5 set_fp_exceptions;