2a1755e30eb6db78cc1a43cb91e3796344545a82
[riscv-isa-sim.git] / riscv / insns / fmin_d.h
1 require_extension('D');
2 require_fp;
3 WRITE_FRD(f64_lt_quiet(f64(FRS1), f64(FRS2)) || isNaNF64UI(FRS2) ? FRS1 : FRS2);
4 if ((isNaNF64UI(FRS1) && isNaNF64UI(FRS2)) || softfloat_exceptionFlags)
5 WRITE_FRD(defaultNaNF64UI);
6 set_fp_exceptions;