d6e1f04ac749d27453ee10f4f2ca874a4b9e3211
[riscv-isa-sim.git] / riscv / insns / fnmadd_d.h
1 require_extension('D');
2 require_fp;
3 softfloat_roundingMode = RM;
4 WRITE_FRD(f64_mulAdd(f64(FRS1 ^ (uint64_t)INT64_MIN), f64(FRS2), f64(FRS3 ^ (uint64_t)INT64_MIN)).v);
5 set_fp_exceptions;