ee74cab2724ee190fb91b7ab58a9fc113f601233
[riscv-isa-sim.git] / riscv / insns / fnmsub_d.h
1 require_extension('D');
2 require_fp;
3 softfloat_roundingMode = RM;
4 WRITE_FRD(f64_mulAdd(f64(FRS1 ^ (uint64_t)INT64_MIN), f64(FRS2), f64(FRS3)).v);
5 set_fp_exceptions;