3e0b8ea7ce37c85e1c6220fdefcc717e0a9cd9ba
[riscv-isa-sim.git] / riscv / insns / fnmsub_s.h
1 require_extension('F');
2 require_fp;
3 softfloat_roundingMode = RM;
4 WRITE_FRD(f32_mulAdd(f32(FRS1 ^ (uint32_t)INT32_MIN), f32(FRS2), f32(FRS3)).v);
5 set_fp_exceptions;