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69b2d98c4b0c4c0de47ba7d6377e660b55e55978
[riscv-isa-sim.git]
/
riscv
/
insns
/
fsgnjx_s.h
1
require_fp
;
2
WRITE_FRD
(
FRS1
^ (
FRS2
& (
uint32_t
)
INT32_MIN
));