238ee9e8fb536148dabb0002820ec75310bcd28d
[riscv-isa-sim.git] / riscv / insns / fsub_d.h
1 require_fp;
2 softfloat_roundingMode = RM;
3 WRITE_FRD(f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2 ^ (uint64_t)INT64_MIN));
4 set_fp_exceptions;