projects
/
riscv-isa-sim.git
/ blob
commit
grep
author
committer
pickaxe
?
search:
re
ec25bc42553b7a097e63d23c89dc24bf0a53690e
[riscv-isa-sim.git]
/
riscv
/
insns
/
lh.h
1
RD
=
mmu
.
load_int16
(
RS1
+
SIMM
);