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2b954195b79b9eca3ca5289b1b1efaf0db6880c5
[riscv-isa-sim.git]
/
riscv
/
insns
/
lr_w.h
1
p
->
get_state
()->
load_reservation
=
RS1
;
2
WRITE_RD
(
MMU
.
load_int32
(
RS1
));